;bdiGDB configuration file for Xilinx V2P core
; --------------------------------------------
;
; The 405 cores are daisy chanined with the FPGA
;
[INIT]
; init core register
#0 WSPR	954	0x00000000      ;DCWR: Disable data cache write-thru
#0 WSPR	1018	0x00000000	;DCCR: Disable data cache
#0 WSPR	1019	0x00000000	;ICCR: Disable instruction cache
#0 WSPR 982	0x00000000	;EVPR: Exception Vector Table @0x00000000

#1 WSPR	954	0x00000000      ;DCWR: Disable data cache write-thru
#1 WSPR	1018	0x00000000	;DCCR: Disable data cache
#1 WSPR	1019	0x00000000	;ICCR: Disable instruction cache
#1 WSPR 982	0x00000000	;EVPR: Exception Vector Table @0x00000000


[TARGET]
JTAGCLOCK       0               ;use 16 MHz JTAG clock
POWERUP         4000            ;give target time to power-up

#0 CPUTYPE      405 		;the used target CPU type
#0 SCANPRED     2 16            ;XC18V04 + XC18V04
#0 SCANSUCC     1 10            ;405 + FPGA
#0 SCANMISC     4 0xE0          ;IR length = 4, IR LSB = ..100000
#0 BREAKMODE    HARD            ;SOFT or HARD, HARD uses PPC hardware breakpoint
#0 STEPMODE     HWBP            ;JTAG or HWBP, HWPB uses one or two hardware breakpoints

#1 CPUTYPE      405 		;the used target CPU type
#1 SCANPRED     3 20            ;XC18V04 + XC18V04 + 405
#1 SCANSUCC     0 6             ;FPGA
#1 SCANMISC     4 0xE0          ;IR length = 4, IR LSB = ..100000
#1 BREAKMODE    HARD            ;SOFT or HARD, HARD uses PPC hardware breakpoint
#1 STEPMODE     HWBP            ;JTAG or HWBP, HWPB uses one or two hardware breakpoints

[HOST]
IP          151.120.25.119

#0 FILE     E:\cygwin\home\demo\mpc860\fibo.elf
#0 FORMAT   ELF
#0 LOAD     MANUAL              ;load code MANUAL or AUTO after reset

#1 FILE     E:\cygwin\home\demo\mpc860\fibo.elf
#1 FORMAT   ELF
#1 LOAD     MANUAL              ;load code MANUAL or AUTO after reset


[FLASH]


[REGS]
#0 IDCR1	0x010	0x01    ;MEMCFGADR and MEMCFGDATA
#0 IDCR2	0x012	0x013	;EBCCFGADR and EBCCFGDATA
#0 IDCR3	0x014	0x015	;KIAR and KIDR
#0 FILE         E:\cygwin\home\bdidemo\evb405\reg405.def

#1 IDCR1	0x010	0x011	;MEMCFGADR and MEMCFGDATA
#1 IDCR2	0x012	0x013	;EBCCFGADR and EBCCFGDATA
#1 IDCR3        0x014	0x015	;KIAR and KIDR
#1 FILE         E:\cygwin\home\bdidemo\evb405\reg405.def