;bdiGDB configuration file for Xilinx ML403 Reference Board ; ------------------------------------------------------ ; [INIT] ; init core register WSPR 954 0x00000000 ;DCWR: Disable data cache write-thru WSPR 1018 0x00000000 ;DCCR: Disable data cache WSPR 1019 0x00000000 ;ICCR: Disable instruction cache WSPR 982 0x00000000 ;EVPR: Exception Vector Table @0x00000000 ; Setup Peripheral Bus ;WDCR 18 0x00000010 ;Select PB0AP ;WDCR 19 0x9B015480 ;PB0AP: Flash and SRAM ;WDCR 18 0x00000000 ;Select PB0CR ;WDCR 19 0xFFF18000 ;PB0CR: 1MB at 0xFFF00000, r/w, 8bit ;WDCR 18 0x00000011 ;Select PB1AP ;WDCR 19 0x02815480 ;PB1AP: NVRAM and RTC ;WDCR 18 0x00000001 ;Select PB1CR ;WDCR 19 0xF0018000 ;PB1CR: 1MB at 0xF0000000, r/w, 8bit ;WDCR 18 0x00000012 ;Select PB2AP ;WDCR 19 0x04815A80 ;PB2AP: Keyboard and Mouse ;WDCR 18 0x00000002 ;Select PB2CR ;WDCR 19 0xF0118000 ;PB2CR: 1MB at 0xF0100000, r/w, 8bit ;WDCR 18 0x00000013 ;Select PB3AP ;WDCR 19 0x01815280 ;PB3AP: IRDA ;WDCR 18 0x00000003 ;Select PB3CR ;WDCR 19 0xF0218000 ;PB3CR: 1MB at 0xF0200000, r/w, 8bit ;WDCR 18 0x00000017 ;Select PB7AP ;WDCR 19 0x01815280 ;PB7AP: FPGA ;WDCR 18 0x00000007 ;Select PB7CR ;WDCR 19 0xF0318000 ;PB7CR: 1MB at 0xF0300000, r/w, 8bit ; Setup SDRAM Controller ;WDCR 16 0x00000080 ;Select SDTR1 ;WDCR 17 0x0086400D ;SDTR1: SDRAM Timing Register ;WDCR 16 0x00000040 ;Select MB0CF ;WDCR 17 0x00046001 ;MB0CF: 16MB @ 0x00000000 ;WDCR 16 0x00000048 ;Select MB2CF ;WDCR 17 0x01046001 ;MB2CF: 16MB @ 0x01000000 ;WDCR 16 0x00000030 ;Select RTR ;WDCR 17 0x05F00000 ;RTR: Refresh Timing Register ;WDCR 16 0x00000020 ;Select MCOPT1 ;WDCR 17 0x80800000 ;MCOPT1: Enable SDRAM Controller ; Setup MMU info ;WM32 0x000000f4 0x00000000 ;invalidate kernel page table base ;WM32 0x000000f8 0x00000000 ;invalidate process page table base ;WM32 0x000000f0 0xc00000f4 ;invalidate page table base [TARGET] CPUTYPE 405 ;the used target CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock RESET SYSTEM ;reset type when reset through JTAG BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) WAKEUP 3000 ;wakeup time after reset STARTUP RESET ;state to be in at startup (i.e. after reset) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint ;STEPMODE HWBP ;JTAG or HWBP, HWPB uses one or two hardware breakpoints STEPMODE JTAG ;JTAG or HWBP, HWPB uses one or two hardware breakpoints ;VECTOR CATCH ;catch unhandled exceptions MMU XLAT 0xC0000000 ;enable virtual address mode PTBASE 0x000000f0 ;address where kernel/user stores pointer to page table ;SIO 7 9600 ;TCP port for serial IO ;REGLIST SPR ;select register to transfer to GDB ;REGLIST ALL ;select register to transfer to GDB ;for virtex4 -> System Ace, XCF32P, FPGA and XC95144xl SCANPRED 2 24 ;JTAG devices connected before PPC405: 8 (SYSTEM ACE) + 16 (XCF32P): SCANSUCC 1 14 ;JTAG devices connected after PPC405: 6 (FPGA) + 8 (XC95144xl) SCANMISC 4 0xE0 8 ; IR length = 4 IR LSB = ..10000011111111. 8 is used in this ; instruction as PPC405 is not the last device on the JTAG ; chain and so the padding infomation is needed for using ; ..100000 for PPC405. ; --------------------------------------------------------------------- ; stand-alone JTAG chain ; first CPU in AFX 2VP20 board ;SCANPRED 0 0 ;SCANSUCC 1 4 ;SCANMISC 4 ; second CPU in AFX 2VP20 board ;SCANPRED 1 4 ;SCANSUCC 0 0 ;SCANMISC 4 ; combined JTAG chain ; first CPU in AFX 2VP20 board ;SCANPRED 2 16 ;SCANSUCC 1 10 ;SCANMISC 4 0xE0 ; second CPU in AFX 2VP20 board ;SCANPRED 3 20 ;SCANSUCC 0 6 ;SCANMISC 4 0xE0 ; ---------------------------------------------------------------------- [HOST] ;IP 151.120.25.118 ;Linux host IP 149.199.109.4 ;Windows host ;tftpsrv root dir must be properly set for this to work FILE H:\bdi\zImage.initrd.elf FORMAT ELF START 0x00400000 LOAD MANUAL ;load code MANUAL or AUTO after reset DEBUGPORT 2001 DUMP C:\Projects\BDI_tools\dump.bin ;DUMP dump.bin ;Linux: dump.bin must already exist and public writable PROMPT bdi> ;custom prompt [FLASH] ;WORKSPACE 0x00004000 ;workspace in target RAM for fast programming algorithm ;CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) ;CHIPSIZE 0x80000 ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000) ;BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32) ;FILE ;The file to program ;ERASE 0xFFF80000 ;erase sector 0 of flash in U7 (AM29F040) ;ERASE 0xFFF90000 ;erase sector 1 of flash ;ERASE 0xFFFA0000 ;erase sector 2 of flash ;ERASE 0xFFFB0000 ;erase sector 3 of flash ;ERASE 0xFFFC0000 ;erase sector 4 of flash ;ERASE 0xFFFD0000 ;erase sector 5 of flash ;ERASE 0xFFFE0000 ;erase sector 6 of flash ;ERASE 0xFFFF0000 ;erase sector 7 of flash [REGS] ;IDCR1 0x010 0x011 ;MEMCFGADR and MEMCFGDATA ;IDCR2 0x012 0x013 ;EBCCFGADR and EBCCFGDATA ;IDCR3 0x014 0x015 ;KIAR and KIDR ;FILE \reg405gp.def ;FILE C:\Projects\BDI_tools\reg405gp.def