; bdiGDB configuration for H4 menelaus chip with mDDR combo part. ; -------------------------------------------------------------- ; Because the RESET signal is not routed to the Multi-ICE ; connector, it is not possible for the BDI to force a reset. ; Also it is not possible to stop the target immediatelly at ; the reset vector. To get control of the board, power-cycle it ; or press the reset button on the Processor Module and then ; enter reset at the BDI2000 Telnet interface. ; ; [INIT] ; WREG CPSR 0x000000d3 ;set superviser mode WGPR 15 0x48000000 ;set PC WCP15 0x0001 0x00050078 ;CP15 Control : disable caches ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Stuff from linux_connect.cmm ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; WM32 0x48022048 0x0000AAAA ; WM32 0x48022048 0x00005555 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; STUFF from setup_dpll.cmm ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;DPLL out = 2x DPLL --> core clock WM32 0x48008544 0x00000002 ; CM_CLKSEL2_PLL ; DPLL into low power bypass (others off) WM32 0x48008500 0x00000001 ; CM_CLKEN_PLL DELAY 0x10 ; MPU core clock = Core /2 = 300 WM32 0x48008140 0x00000002 ; CM_CLKSEL_MPU ; DSPif=, DSPif=, IVA= WM32 0x48008840 0x00000343 ; CM_CLKSEL_DSP ; GFX clock WM32 0x48008340 0x00000002 ; CM_CLKSEL_GFX ; L3=, L4=, DisplaySS=55 Vlync=,ssi=, usb WM32 0x48008240 0x04600C26 ; CM_CLKSEL1_CORE ; Check 0x48008084 to make sure valid ;12MHz apll src, WM32 0x48008540 0x01832100 ; CM_CLKSEL1_DPLL ; Valid the configuration WM32 0x48008080 0x00000001 ; CLKCFG_CTRL DELAY 0x50 ; Enable DPLL=330, 96MHz APLL locked. WM32 0x48008500 0x0000000F ; CM_CLKEN_PLL DELAY 0x100 ; Check if configuration valid ;data.dump 0x48008084 /long ; CLKCFG_STATUS ;data.dump 0x48008520 /long ; CLKCFG_STATUS ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Stuff from linux_sdram_32bit.cmm ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Example script file for ARM1136JF on ZeBu ; 16.09.03, PEG ; pin Muxing for SDRC WM32 0x480000A1 0x10 ; ball C12, mode 0 WM32 0x48000032 0x10 ; ball D11, mode 0 ; configure sdrc 16 bit for COMBO ddr sdram WM32 0x68009010 0x00000012 DELAY 100 WM32 0x68009010 0x00000010 WM32 0x68009044 0x00000100; Chip-level shared interface management ; SDRCTriState: no Tris ; CS0MuxCfg: 000 (32-bit SDRAM on D31..0) ; CS1MuxCfg: 000 (32-bit SDRAM on D31..0) ; SDRC_CS0 Configuration ;----------------------- WM32 0x68009080 0x00801011; CS0 SDRC Memory Configuration, ; DDR-SDRAM, External SDRAM is x32bit, ; Configure to MUX24: 16Mbx32 WM32 0x6800909c 0x5A59B485 WM32 0x680090A0 0x0000000E WM32 0x680090A4 0x00002401 ;Manual Command sequence WM32 0x680090A8 0x00000000 WM32 0x680090A8 0x00000001 WM32 0x680090A8 0x00000002 WM32 0x680090A8 0x00000002 WM32 0x68009084 0x00000032; CS0 SDRC Mode Register ; Burst length = 4 - DDR memory ; Serial mode ; CAS latency = 3 ; /* SDRC DLLA control register */ ; /* Enable DLL, Load counter with 115 (middle of range) */ ; /* Delay is 90 degrees */ WM32 0x68009060 0x0000980c WM32 0x68009060 0x00009808 ;; es1 WM32 0x68009060 0x2 ; /* SDRC DLLB control register */ ; /* Enable DLL, Load counter with 128 (middle of range) */ ; /* Delay is 90 degrees */ WM32 0x68009068 0x0000980c ;/* load ctr value */ WM32 0x68009068 0x00009808 ;/* lock and go */ ;; es1 WM32 0x68009068 0x2 ;REPEAT 0x100 ;( ;wait 1.ms ;) DELAY 100 ;Dumps for convenience ;data.dump 0x68009000 /long ; display SDRC controls ;data.dump 0x80000000 /word ; display SDRC ;pin mux for GPMC_IO_DIR WM32 0x4800008C 0x19000000 ; Added from NOR Flash CMM from Satish - 26/Jun/04 ;GPMC ; configure GPMC ; configure CS0, NOR FLASH WM32 0x6800A010 0x00000000 WM32 0x6800A01C 0x00000000 ;; es1 WM32 0x6800A040 0x00000001 WM32 0x6800A050 0x00000111 ;added by nts 30/Jun/04 WM32 0x6800A068 0x00030301 WM32 0x6800A06C 0x0C030C03 ; david ;added by nts 30/Jun/04 WM32 0x6800A078 0x00000C44 ; base 0x04000000 WM32 0x6800A060 0x00001203 ;changed by nts - 30/Jun/04 ; configure CS1, Multiport Debug Board WM32 0x6800A090 0x00011200; /*Muxed data/address (NOR flash) interface*/ WM32 0x6800A094 0x001F1F00; /*Set CS for maximum width*/ WM32 0x6800A098 0x00080802; /*Set ADV for 6 clocks*/ WM32 0x6800A09C 0x1C091C09; /*WE and OE timing are set for mux mode*/ WM32 0x6800A0A0 0x031A1F1F; WM32 0x6800A0A4 0x000003C2; WM32 0x6800A0A8 0x00000F48; //base 0x08000000 [TARGET] CPUTYPE ARM1136 CLOCK 5 ;JTAG clock : without adaptive clocking cable POWERUP 3000 ;start delay after power-up detected in ms SCANPRED 1 2 ;JTAG devices connected before this core SCANSUCC 1 4 ;JTAG devices connected after this core TRST PUSHPULL ;TRST driver type (OPENDRAIN | PUSHPULL) RESET HARD ;NONE | HARD (ms) ENDIAN LITTLE ;memory model (LITTLE | BIG) ;VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset BREAKMODE HARD ;SOFT or HARD, ARM / Thumb break code ;BREAKMODE SOFT 0xDFFFDFFF ;SOFT or HARD, ARM / Thumb break code STARTUP RESET [HOST] IP 172.24.190.5 FILE C:\u-boot ; for download test only FORMAT ELF ;don't overwrite translation table LOAD AUTO ;load code MANUAL or AUTO after reset ;LOAD MANUAL ;load code MANUAL or AUTO after reset [FLASH] [REGS] FILE C:\Abatron.new\reg1136.def