; bdiGDB configuration for H4 menelaus chip Direct Connect.
; --------------------------------------------------------------
; Because the RESET signal is not routed to the Multi-ICE
; connector, it is not possible for the BDI to force a reset.
; Also it is not possible to stop the target immediatelly at
; the reset vector. To get control of the board, power-cycle it
; or press the reset button on the Processor Module and then
; enter reset at the BDI2000 Telnet interface.
;
;
[INIT]
;
WREG    CPSR        0x000000d3  ;set superviser mode
WGPR    15          0x48000000  ;set PC
WCP15   0x0001      0x00050078  ;CP15 Control : disable caches
;

[TARGET]
CPUTYPE     ARM1136
CLOCK       5                   ;JTAG clock : without adaptive clocking cable
POWERUP     3000                ;start delay after power-up detected in ms
SCANPRED    1 2                 ;JTAG devices connected before this core
SCANSUCC    1 4                ;JTAG devices connected after this core
TRST        PUSHPULL           ;TRST driver type (OPENDRAIN | PUSHPULL)
RESET	    HARD	        ;NONE | HARD <n> (ms)
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
;VECTOR      CATCH 0x1f          ;catch D_Abort, P_Abort, SWI, Undef and Reset
BREAKMODE   HARD	        ;SOFT or HARD, ARM / Thumb break code
;BREAKMODE  SOFT 0xDFFFDFFF     ;SOFT or HARD, ARM / Thumb break code
STARTUP     RESET


[HOST]
IP          10.0.4.45
FILE        zImage
FORMAT      ELF	     ;don't overwrite translation table
;LOAD        AUTO      ;load code MANUAL or AUTO after reset
LOAD        MANUAL      ;load code MANUAL or AUTO after reset

[FLASH]
CHIPTYPE	STRATAX16
CHIPSIZE	0x2000000
BUSWIDTH	16
WORKSPACE	0x4020f800

[REGS]
FILE	    reg1136.def