; bdiGDB configuration for Motorola M9328MX2ADS board
; ---------------------------------------------------
;
[INIT]
;
; Initialize DragonBall i.MX21 ADS Rev 0.1 board when using JTAG
; so SRAM and SDRAM are downloadable
;
WM32    0xDF001000  0x00000600 ; CS0 - boot flash configured like the linux kernel 
WM32    0xDF001004  0x00000e01
WM32    0xDF001008  0x00002000 ; CS1 - SDRAM, configured like the linux kernel
WM32	0xDF00100C  0x11118501

; Address translation for integrated peripherals.
WM32    0x10000000  0x00040304 ; Set up address translation between the AHB and IP buses
WM32	0x10020000  0x3FFC0000 ; more address info
WM32    0x10000004  0xFFFBFCFB ; more address info
WM32    0x10020004  0xFFFFFFFF ; more address info
WM32    0x10000008  0xFF000000 ; Now define which peripherals exist
WM32 	0x10020008  0xFFFFFF00

; Setup the PLL and clocks
WM32 	0x10027004  0x007B1C73 ; MPLL setup 1 
WM32 	0x10027008  0x00000040 ; MPLL setup 2 
WM32 	0x1002700C  0x03B02227 ; Set up spll for 287.9999978Mhz operation
WM32 	0x10027000  0x17000607 ; 
WM32	0x10027020  0x44042800 ; Enable HCLK_DMA, LCDC, LCD_PIXCLK, DMA_EN, GPIO_EN.  Modify this if you want to talk to other integrated peripherals.

;
;Init SDRAM 16Mx16x2 IAM0 CS2 CL2
;
WM32    0xDF000000  0x92120200  ;Set Precharge Command , FIXME: Verify SCL,SRCD and SRC bits are correct with SDRAM datasheet
WM32    0xC0200000  0x00000000  ;Issue Precharge all Command
WM32    0xDF000000  0xa2120200  ;Set AutoRefresh Command
WM32    0xC0000000  0x00000000  ;Issue AutoRefresh Command
WM32    0xC0000000  0x00000000
WM32    0xC0000000  0x00000000
WM32    0xC0000000  0x00000000
WM32    0xC0000000  0x00000000
WM32    0xC0000000  0x00000000
WM32    0xC0000000  0x00000000
WM32    0xC0000000  0x00000000
WM32    0xDF000000  0xb2120200  ;Set Mode Register
WM32    0xC0111800  0x00000000  ;Issue Mode Register Command, Burst Length = 8, FIXME: Look at our datasheet
WM32    0xDF000000  0x82124200  ;Set to Normal Mode

; DELAY 10
; LCD Controller

; WM32  0x10021000 0xc0359000
; WM32  0x10021004 0x00f00140
; WM32  0x10021008 0x00000078
; WM32  0x1002100C 0x00000000
; WM32  0x10021010 0x010100ff
; WM32  0x10021014 0x00000000
; WM32  0x10021018 0xfb108bc7
; WM32  0x1002101C 0x04000f06
; WM32  0x10021020 0x04000907
; WM32  0x10021024 0x00000000
; WM32  0x10021028 0x00120300
; WM32  0x1002102C 0x00a903c8
; WM32  0x10021030 0x0004000f
; WM32  0x10021034 0x00000000
; WM32  0x10021038 0x00000000
; WM32  0x1002103C 0x00000000
; WM32  0x10021040 0x0000000f
; WM32  0x10021050 0x00000000
; WM32  0x10021054 0x00000000
; WM32  0x10021058 0x00000000
; WM32  0x1002105C 0x00000000
; WM32  0x10021060 0x00000000
; WM32  0x10021064 0x00000000
; WM32  0x10021068 0x80100004

;

[TARGET]
CPUTYPE     ARM926E
CLOCK       4                   ;JTAG clock (0=Adaptive, 1=16MHz, 2=8MHz, 3=4MHz, 4=1MHz, ...)
WAKEUP      10000                ;because of slow rising reset line
RESET       HARD 1000           ;beause of heavy capacitive load on reset line
TRST        PUSHPULL            ; 
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE   SOFT 0xDFFFDFFF     ;SOFT or HARD, ARM / Thumb break code
;VECTOR      CATCH 0x1f          ;catch D_Abort, P_Abort, SWI, Undef and Reset
;SIO         7 9600              ;TCP port for serial IO
;DCC         7                   ;TCP port for DCC I/O

[HOST]
IP 172.16.168.71
FILE        /tftpboot/bootloader.bin
FORMAT      BIN
LOAD        MANUAL      ;load VxWorks code MANUAL or AUTO after reset
START 0xC2000000

[FLASH]

CHIPTYPE AM29BX16
CHIPSIZE 0x1000000
BUSWIDTH 32
FILE /tftpboot/blob.bootloader
FORMAT BIN 0xC8000000
; WORKSPACE 0xC0000000 

[REGS]
FILE	/tftpboot/regMX2.def