[INIT]
; [DISABLED] init core register
;WREG    MSR             0x00001002      ;MSR  : ME,RI

;Keep MMBAR at 0xFF400000
WM32	0xff400000	0xFF400000

; ===========================================
; System Configuration - Local Access Windows 
; ===========================================

; Local Bus Local Access Windows
; ==============================
; WINDOW 0 - Initially mapped by RCWHR[BMS], relocated to 0xff400000
WM32 0xff400020 0xff400000 ; LBLAWBAR0  - start at 0xff400000

; WINDOW 1
WM32 0xff400028 0xf8000000 ; LBLAWBAR1  - start at 0xf8000000
WM32 0xff40002c 0x8000001a ; LBLAWAR1   - enable, size = 128MB 

; PCI Local Access Windows
; ========================
; WINDOW 0
WM32 0xff400060 0x80000000 ; PCILAWBAR0 - start at 0x80000000
WM32 0xff400064 0x8000001c ; PCILAWAR0  - enable, size = 512MB

; WINDOW 1
WM32 0xff400068 0xa0000000 ; PCILAWBAR1 - start at 0xa0000000
WM32 0xff40006c 0x8000001c ; PCILAWAR1  - enable, size = 512MB

; DDR Local Access Windows
; ========================
; WINDOW 0 - 1st DDR SODIMM
WM32 0xff4000a0 0x00000000 ; DDRLAWBAR0 - start at 0x00000000
WM32 0xff4000a4 0x8000001b ; DDRLAWAR0  - enable, size = 256MB

; WINDOW 1 - 2nd DDR SODIMM
WM32 0xff4000a8 0x10000000 ; DDRLAWBAR1 - start at 0x10000000
WM32 0xff4000ac 0x8000001b ; DDRLAWAR1  - enable, size = 256MB

; ============================
; DDR Controller Configuration
; ============================

; CS0_CONFIG
WM32 0xff402080 0x80000102

; CASLAT = 1.5
WM32 0xff402108 0x37324321

; TIMING_CONFIG_2
WM32 0xff40210C 0x00000800

; Temporarily disable the memory interface for reconfiguration
WM32 0xff402110 0x42000000

; CASLAT = 2
WM32 0xff402118 0x00000022

; DDR_SDRAM_INTERVAL
WM32 0xff402124 0x04060100

; 8347PC : sdram_clk_cntl : Source Sync mode enable SS_EN=1, 
; CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM clock cycle after 
; address/command 
WM32 0xff402130 0x82000000

delay 300

; enable the DDR memory controller
WM32 0xff402110 0xc2000000 


; =============================================
; Local Bus Interface (LBIU) Configuration
; =============================================

; CS0 - 16MB FLASH 
WM32 0xff405000 0xfe001001 ; BR0 base address at 0xFe000000, port size 16 bit, GPCM, valid
WM32 0xff405004 0xff006ff7 ; OR0 16MB flash size (two 8M), 15 w.s., timing relaxed

; CS1 - board VSC7385
WM32 0xff405008 0xf8000801 ; BR1 base address at 0xFE400000, port size 8 bit, GPCM, valid
WM32 0xff40500c 0xfffe09ff ; OR1 128KB size, 15 w.s., timing relaxed, external TA

; CS2 - LED & Board ID
WM32 0xff405014 0xffe0ef97 ; OR2 128KB size
WM32 0xff405010 0xf8000801 ; BR2 base address at 0xF8000000, port size 8 bit, GPCM, valid


; LBCR - local bus enable
WM32 0xff4050d0 0x00000000

; LCRR
WM32 0xff4050d4 0x00030004

WREG MSR 0x3000 ;machine check enable, exception vectors at 0x0000_0000

WM32 0xff400800 0x00000000 ; ACR

[TARGET]
CPUTYPE     8349                        ;the CPU type
JTAGCLOCK   2                           ;use 16 MHz JTAG clock
POWERUP     2000                        ;start delay after power-up detected in ms
WAKEUP      500                         ;give reset time to complete
STARTUP     RESET                       ;halt immediately at the boot vector
RCW         0xB060A000 0x04040000       ;override reset configuration words
BOOTADDR    0x00000100                  ;boot address used for start-up break
BREAKMODE   SOFT      	                ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP                        ;TRACE or HWBP, HWBP uses a hardware breakpoint

[FLASH]
CHIPTYPE    AM29BX16    ;Flash type: Macronix MX29LV640BTTC-90G
CHIPSIZE    0x800000  	;The size of one flash chip in bytes
BUSWIDTH    16          ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)

[REGS]
FILE        $reg8349e.def