[INIT]
; =========================================
; 	AHB-Lite IP Interface  
; =========================================
WM32 0x10000000 0x20040304
WM32 0x10020000 0x00000000
WM32 0x10000004 0xDFFBFCFB
WM32 0x10020004 0xFFFFFFFF

; =========================================
;    INIT CLK
; =========================================
;For 32k clock as PLL input
WM32 0x10027000 0x33f00307
;output MPLL_CLK / 8 on CLKO
WM32 0x10027018 0x13c401c3
WM32 0x10027028 0x00000000


WM32 0x10027000 0x33f00304
WM32 0x10027000 0x33f30307
;restart PLL for 266MHz (TO1 issue => default at 272MHz)
WM32 0x10027004 0x00331c23
WM32 0x10027000 0x33f38107

DELAY 100

; ========================================
;  Configure DDR on CSD0 -- initial reset
; ========================================
WM32 0xD8001010 0x80000000

; =========================================
;   WEIM WCR REGISTER
; =========================================
WM32 0xD8002060  0x00001000

; ========================================
;  Configure PSRAM on CS5 
; ========================================
WM32 0xD8002050 0x0000DCf6
WM32 0xD8002054 0x444A4541
WM32 0xD8002058 0x44443302

;  ========================================
;         Configure16 bit NorFlash on CS0
;  ========================================
WM32 0xD8002000 0x0000CC03
WM32 0xD8002004 0xa0330D01
WM32 0xD8002008 0x00220800

; ========================================
;  Configure CPLD on CS4 
; ========================================
WM32 0xD8002040 0x0000DCF6
WM32 0xD8002044 0x444A4541
WM32 0xD8002048 0x44443302

; ========================================
;  Configure DDR on CSD0 -- wait 5000 cycle 
; ========================================
WM32 0x10027828 0x55555555
WM32 0x10027830 0x55555555
WM32 0x10027834 0x55555555
WM32 0x10027838 0x00005005
WM32 0x1002783C 0x15555555
WM32 0xD8001010 0x80000004
WM32 0xD8001004 0x00795429
WM32 0xD8001000 0x92200000
DELAY 100
WM32 0xA0000F00 0x00000000
WM32 0xD8001000 0xA2200000
DELAY 100
WM32 0xA0000F00 0x00000000
WM32 0xD8001000 0xB2200000
DELAY 100
WM8  0xA0000033 0x00
DELAY 100
WM8  0xA1000000 0x00
WM32 0xD8001000 0x82228485
WM32 0xD8001000 0x82228485

; Set ARM mode
WREG CPSR 0x000000D3

[TARGET]
CPUTYPE	ARM926E
CLOCK		1                   ;JTAG clock (0=Adaptive, 1=8MHz, 2=4MHz, 3=2MHz)
WAKEUP	500                ;because of slow rising reset line
RESET		HARD 100            ;beause of heavy capacitive load on reset line
;RESET		HARD            ;beause of heavy capacitive load on reset line
ENDIAN	LITTLE              ;memory model (LITTLE | BIG)
BREAKMODE	SOFT 0xDFFFDFFF     ;SOFT or HARD, ARM / Thumb break code
;VECTOR	CATCH 0x1f          ;catch D_Abort, P_Abort, SWI, Undef and Reset
;SIO		7 9600              ;TCP port for serial IO
;DCC		7                   ;TCP port for DCC I/O
SCANPRED	0 0			;
SCANSUCC	1 4			; the ETMBUF after the ARM926 core
STARTUP	RESET			; the ARM 926 core is stop after reset

[HOST]
IP		192.168.0.33
;IP		192.168.0.64
PROMPT	MX27-PC>
;FILE		MX27_DMAC_test_NOR_Synch_mode.bin
;FILE		i.MX27_LCDC-Camera_emulator.bin
FILE		redboot.bin
;FILE		redboot.elf
FORMAT	BIN 0xa0000000
;FORMAT	ELF 0xFFFF4C00
START		0xa0000000
LOAD		MANUAL      ;load code MANUAL or AUTO after reset

[FLASH]


[REGS]
FILE    reg926e.def