; bdiGDB configuration file for iMX25PDK
; --------------------------------------
;
; Info about the JTAG clock frequency:
; ------------------------------------
; BDI2000:
;   0=Adaptive,
;   1=16MHz, 2=8MHz, 3=4MHz,
;   4= 1MHz, 5=500kHz, 6=200kHz, 7=100kHz, 8=50kHz,
;   9=20kHz, 10=10kHz, 11=5kHz, 12=2kHz, 13=1kHz
; BDI3000:
;   0=Adaptive,
;   1=32MHz, 2=16MHz, 3=11MHz, 4=8MHz, 5=5MHz, 6=4MHz,
;   7=1MHz, 8=500kHz, 9=200kHz, 10=100kHz, 11=50kHz,
;   12=20kHz, 13=10kHz, 14=5kHz, 15=2kHz, 16=1kHz,
;


[INIT]

WREG    CPSR        0x000000D3
WCP15   0x001       0x00000078  ;CPACC: allow CP10 and CP11 access
WM32    0xB8001010  0x00000004

;******************************************************************************
;** 	ESDRAMC Timing  (Subject to Change)
;******************************************************************************
WM32 0xb8001004	0x006ac73a

;******************************************************************************
;**	Initialize Mobile DDR Section
;******************************************************************************

;***************    Enable Precharge Command   ***************
WM32 0xb8001000	0x92100000

;***************    Precharge All	       *****************
WM32 0x80000400	0x12344321

;***************    Enable Auto Refresh Command   ***************
WM32 0xb8001000	0xa2100000
WM32 0x80000000	0x12344321
WM32 0x80000000	0x12344321

;***************    Load Mode Register command   ***************
;***************    CAS3, Burst Length 8 since 16 bit mem  *********
WM32 0xb8001000	0xb2100000
WM8  0x80000033 0xda
WM8  0x81000000 0xff

;***************    13 Rows, 10 Col, Refresh = 8192 cycles in 64mS   ***************
WM32 0xb8001000	0x82216880

;******************************************************************************
;**	End of Mobile DDR INIT
;******************************************************************************

;******************************************************************************
;**	Configure AIPS1 and 2
;******************************************************************************

WM32 0x43f00040	0x0
WM32 0x43f00044	0x0
WM32 0x43f00048	0x0
WM32 0x43f0004c	0x0
WM32 0x43f00050	0x0

WM32 0x43f00000	0x77777777
WM32 0x43f00004	0x77777777

WM32 0x53f00040	0x0
WM32 0x53f00044	0x0
WM32 0x53f00048	0x0
WM32 0x53f0004c	0x0
WM32 0x53f00050	0x0

WM32 0x53f00000	0x77777777
WM32 0x53f00004	0x77777777

;******************************************************************************
;**	Configure CS5 for CPLD
;******************************************************************************
WM32 0xb8002050	0x0000d843	;CS5_CSCRU
WM32 0xb8002054	0x22252521	;CS5_CSCRL
WM32 0xb8002058 0x22220a00	;CS5_CSCRA

;******************************************************************************
;**	Init Clock Control Module
;******************************************************************************

WM32 0x53f80008	0x20034000	;ARM=399, AHB=133




[TARGET]
CPUTYPE	        ARM926E
CLOCK		4               ;BDI3000: 8 MHz
WAKEUP		500
RESET		HARD 500        ;beause of heavy capacitive load on reset line
ENDIAN		LITTLE          ;memory model (LITTLE | BIG)
BREAKMODE	SOFT 0xDFFFDFFF ;SOFT or HARD, ARM / Thumb break code
;
SCANPRED	2 9		;SJC and SDMA
SCANSUCC	1 4	        ;ETMBUF after the ARM926 core
;
SCANINIT  t1:w1000:t0:w1000:    ;toggle TRST,
SCANINIT  ch5:w10000            ;clock TCK with TMS high and wait
;


[HOST]
IP		192.168.1.133
PROMPT	        MX25PDK>


[FLASH]


[REGS]
FILE    reg926e.def