;bdiGDB configuration file for FREESCALE CDS8548 ;-------------------------------------------------- ; ; Use default boot configuration: ; - Boot sequencer disabled ; - Boot from local bus 16-bit Flash ; ;cds8548>l2cam 0 0xf ;Current Mapping of CDS8548 ; ;IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS ; 0 : 00 ff000000 16MB V 0 -> 0_ff000000 0000 -I-G- ---RWX ; 1 : 00 00000000 256MB V 0 -> 0_00000000 0000 --M-- ---RWX ; 2 : 00 e0000000 1MB V 0 -> 0_e0000000 0000 -I-G- ---RW- ; 3 : 00 e0000000 1MB V 1 -> 0_e0000000 0000 -I-G- ---RW- ; 4 : 00 f0000000 64MB V 0 -> 0_f0000000 0000 --M-- ---RWX ; 5 : 00 f7000000 16MB V 0 -> 0_f7000000 0000 -IMG- ---RW- ; [INIT] ; load TLB entries, helper code @ 0xfffff000 WM32 0xfffff000 0x7c0007a4 ;tlbwe WM32 0xfffff004 0x7c0004ac ;msync WM32 0xfffff008 0x48000000 ;loop ; ; 16MB TLB1 #0 0xff000000 - 0xffffffff (FLASH BOOT/2nd Bank) WSPR 624 0x10000000 ;MAS0: WSPR 625 0xc0000700 ;MAS1: WSPR 626 0xff00022a ;MAS2: WSPR 627 0xff000015 ;MAS3: EXEC 0xfffff000 ; ; 256MB TLB1 #1 0x00000000 - 0x0fffffff (Main Memory) WSPR 624 0x10010000 ;MAS0: WSPR 625 0xc0000900 ;MAS1: WSPR 626 0x00000224 ;MAS2: WSPR 627 0x00000015 ;MAS3: EXEC 0xfffff000 ; ; 1 MB TLB1 #2 0xe0000000 - 0xe00fffff (TS=0) WSPR 624 0x10020000 ;MAS0: WSPR 625 0xc0000500 ;MAS1: WSPR 626 0xe000022a ;MAS2: WSPR 627 0xe0000005 ;MAS3: EXEC 0xfffff000 ; ; 1 MB TLB1 #3 0xe0000000 - 0xe00fffff (TS=1) WSPR 624 0x10030000 ;MAS0: WSPR 625 0x80001500 ;MAS1: WSPR 626 0xe000022a ;MAS2: WSPR 627 0xe0000005 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #4 0xf0000000 - 0xf3ffffff (LBC SDRAM) WSPR 624 0x10040000 ;MAS0: WSPR 625 0xc0000800 ;MAS1: WSPR 626 0xf0000224 ;MAS2: WSPR 627 0xf0000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #5 0xf7000000 - 0xf7ffffff (NVRAM) WSPR 624 0x10050000 ;MAS0: WSPR 625 0xc0000700 ;MAS1: WSPR 626 0xf700022e ;MAS2: WSPR 627 0xf7000005 ;MAS3: EXEC 0xfffff000 ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x28010000 ;L2CTL WM32 0xFF720000 0x28000000 ;L2CTL ; ; Move CCSRBAR to 0xe0000000 WM32 0xff700000 0x000e0000 ;JW CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's WM32 0xe0000C08 0x000f0000 ;LAWBAR0 :JW @0xf0000000 WM32 0xe0000C10 0x8040001b ;LAWAR0 :JW Local Bus 256MB WM32 0xe0000C28 0x00000000 ;LAWBAR1 :JW @0x00000000 WM32 0xe0000C30 0x80f0001c ;LAWAR1 :JW Local Bus 512MB ; ; Setup DDR (CDS8548, 256MB DDR) WM32 0xe0002000 0x0000000f ;JW CS0_BNDS WM32 0xe0002080 0x80010102 ;JW CS0_CONFIG WM32 0xe0002108 0x4c47a432 ;JW TIMING_CFG_1 WM32 0xe000210C 0x0f984cce ;JW TIMING_CFG_2 WM32 0xe0002110 0x03008000 ;JW DDR_SDRAM_CFG WM32 0xe0002118 0x00400842 ;JW DDR_SDRAM_MODE WM32 0xe0002124 0x08200100 ;JW DDR_SDRAM_IVAL DELAY 200 WM32 0xe0002110 0xc3008000 ;JW DDR_SDRAM_CFG ; ; Setup Flash chip select WM32 0xe0005000 0xff001001 ;JW BR0 WM32 0xe0005004 0xff006ff7 ;JW OR0 ; ; Setup flash programming workspace in L2SRAM ;WM32 0xe0020000 0x68010000 ;L2CTL ;WM32 0xe0020100 0xf0000000 ;L2SRBAR0 ;WM32 0xe0020000 0xA8010000 ;L2CTL ;WSPR 63 0xf0000000 ;IVPR to workspace ;WSPR 415 0x0001500 ;IVOR15 : Debug exception ;WM32 0xf0001500 0x48000000 ;write valid instruction ; ; Setup flash programming workspace in dual port RAM ;WSPR 63 0x40080000 ;IVPR to workspace ;WSPR 415 0x000007F0 ;IVOR15 : Debug exception ;WM32 0x400807F0 0x48000000 ;write valid instruction ; ; Setup for program execution WM32 0xe0020000 0x28010000 ;L2CTL WM32 0xe0020000 0x28000000 ;L2CTL WSPR 63 0xF0000000 ;IVPR to workspace WSPR 406 0x0000700 ;IVOR6 : Program exception WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0x00000700 0x48000000 ;write valid instruction WM32 0x00001500 0x48000000 ;write valid instruction ; ; Clear flash Lock-Bits ;WM32 0xFF800000 0x00600060 ;clear Lock-Bits command ;WM32 0xFF800000 0x00D000D0 ;DELAY 1000 ;needs up to 0.7 sec ;WM32 0xFF800000 0xFFFFFFFF ;set flash to read mode ; ; [TARGET] ; CPUTYPE 8548 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock SCANPRED 0 0 ;JTAG devices colicensennected before this core SCANSUCC 0 0 ;JTAG devices connected after this core ; ; When using ROM to initialize core select 'STARTUP HALT' ; When using cfg file to set TLB select 'STARTUP LOOP' STARTUP LOOP ;Forces loop out of reset ;STARTUP HALT ;halt core while HRESET is asserted ; ; BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 3000 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms ; MEMACCESS SAP ;use SAP or CORE for JTAG memory accesses ; ; Disable this feature for now, GDB has an issue listing the E500 ; Reg list. This is suppose to be fixed in GDB Version 6.3 ;REGLIST E500 ;use GDB for E500 register list layout ; [HOST] IP 127.0.0.1 PROMPT cds8548> ; [FLASH] ; ; Refere to the following Website for a list of supported flash devices ; and the cross reference to types. ; http://www.abatronag.ch/Files/flashsupp27.pdf CHIPTYPE AM29BX16 ;For 8548CDS Unit, Device is AM29LV641D CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8|16|32) FILE //.bin ; FORMAT BIN 0xFFF00000 ERASE 0xFF800000 CHIP; Erase whole Chip ; [REGS] ; Additional Register information FILE //reg8548.def