;bdiGDB configuration file for Sandpoint 8240 evaluation system ;-------------------------------------------------------------- ; NOTE: as per Motorola conventions, all words are byte-swapped ; relative to the user manual. That's right - if the ; manual indicates 0xA1B2C3D4, then this file must say ; WM32 0xD4C3B2A1. ;-------------------------------------------------------------- ; ; last update: 3/8/02 11:30am ; ;-------------------------------------------------------------- [INIT] ; init core register WREG MSR 0x00000000 ;clear MSR ; default, except exceptions jump to 0x000n_nnnn instead of 0xFFFn_nnnn ; init memory controller (based on DINK32) WM32 0xFEC00000 0x80000080 ;select MSAR1 WM32 0xFEE00000 0x00204060 ; banks are on 32MB boundaries WM32 0xFEC00000 0x84000080 ;select MSAR2 WM32 0xFEE00000 0x80a0c0e0 ; WM32 0xFEC00000 0x90000080 ;select MEAR1 WM32 0xFEE00000 0x1f3f5f7f ; WM32 0xFEC00000 0x94000080 ;select MEAR2 WM32 0xFEE00000 0x9fbfdfff ; WM32 0xFEC00000 0xa0000080 ;select MBEN WM8 0xFEE00000 0x01 ; only bank 0 enabled WM32 0xFEC00000 0xa0000080 ;select MPM WM8 0xFEE00003 0x32 ; 48usec @ 66MHz, 32usec @ 100MHz WM32 0xFEC00000 0xf0000080 ;select MCCR1 WM32 0xFEE00000 0x0000a009 ;do not set MEMGO ; 0000 ROMNAL=0. burst read=0+3 cycles, write=0+4 cycles. ; 1001_1 ROMFAL=19. read=19+2 cycles, write=19+2. ; 01 dbus_siz. RCS1, SDRAM = 32 bit. RCS0 = 8 bit. ; 0_ BURST=nonburst timing ; 0 MEMGO=RAM disabled ; 0 SREN=self refresh disabled during sleep mode ; 0 RAM_TYPE=SDRAM ; 0 PCKEN=disables SDRAM parity check/generate ; 0000_0000_0000_00 Bank_7-1_row=unused ; 00 Bank_0_row=12 bits, 4 banks ; ; raw=0x09a00000. byte-swapped=0x0000a009. WM32 0xFEC00000 0xf4000080 ;select MCCR2 WM32 0xFEE00000 0xa00f601e ; ; 000 TS_WAIT_TIMER=5 clocks (read), 6 clocks (write) ; 1_111 ASRISE=15 clocks ; 0_011 ASFALL=3 clocks ; 0_ INLINE_PAR_NOT_ECC=use ECC ; 0 WRITE_PARITY_CHK=write parity check disabled ; 0 INLINE_RD_EN=read parity check disabled ; 0 ECC_EN=disabled ; 0 EDO=standard DRAMs ; 0000_1111_1010_00 REFINT=1000 clocks, a bit less than 64msec/4k rows @ 66MHz ; 0 RSV_PG=four open page mode ; 0 RMW_PAR=read-modify-write parity disabled ; ; raw=0x1e600fa0. byte-swapped=0xa00f601e. WM32 0xFEC00000 0xf8000080 ;select MCCR3 WM32 0xFEE00000 0x00004077 ; BStoPRE=refresh/8=125=00 0111 1101 ; 0111 BStoPRE[2-5] ; 0111 REFREC=7 clocks (refresh to activate) ; 0100 RDLAT=4 clocks (read latency) ; 0 CPX (EDO only) ; 000_0 RAS/6p (EDO only) ; 000 CAS/5 (EDO only) ; 000 CP/4 (EDO only) ; 0_00 CAS/3 (EDO only) ; 00_0 RCD/2 (EDO only) ; 000 RP/1 (EDO only) ; ; raw=0x77400000. byte-swapped=0x00004077. WM32 0xFEC00000 0xfc000080 ;select MCCR4 WM32 0xFEE00000 0x2d331025 ; ; 0010 PREtoACT=2 clocks (precharge to activate) ; 0101 ACTtoPRE=5 clocks (activate to precharge) ; 0 WMODE=four beats per burst ; 0o1 BUF_TYPE=registered buffer mode ; 00oo BStoPRE[0-1] ; 0 REGDIMM=non-registered memory ; 011_0010 SDMODE=3 CAS, sequential, 4 burst ; 0010 ACtoRW=2 clocks (activate to read/write) ; 1101 BStoPRE[6-9] ; ; raw=0x2510322d. byte-swapped=0x2d321025. WM32 0xFEC00000 0xf0000080 ;select MCCR1 WM32 0xFEE00000 0x0000a809 ;now set MEMGO ; mccr1 was 0x09a00000 ; raw=0x09a80000. byte-swapped=0x0000a809. ; WM32 0xFEC00000 0x78000080 ;select EUMBBAR WM32 0xFEE00000 0x000000fc ;Embedded utility memory block at 0xFC000000 ; WM32 0xFEC00000 0xa8000080 ;select PICR1 WM32 0xFEE00000 0x101014ff ;enable write to flash on local bus ; iiii_iiii_ooo reserved ; 1_ RCS0=boot ROM on local proc/memory bus ; o10 PROC_TYPE=603e ; 0 ADDR_MAP=B ; ooo1_ FLASH_WR_EN=flash write enabled ; 0 MCP_EN=machine check disabled ; o0o_ CF_DPARK=processor core not parked on data bus ; o0 ST_GATH_EN=PCI store gathering disabled ; 0i_ LE_MODE=big endian mode ; 0 CF_APARK=processor core not parked on local address bus ; 0oo Speculative PCI Reads disabled ; ; raw=0xff141010. byte-swapped=0x101014ff. ; WM32 0xFEC00000 0xac000080 ;select PICR2 WM32 0xFEE00000 0x00000000 ; ; oo0o NO_SERIAL_CFG=PCI writes are serialized, buffers are flushed ; 0 NO_SNOOP_EN=snooping enabled on PCI-to-memory transactions ; 0 CF_FF0_LOCAL=ROM/Flash remapping disabled (PCI boot only) ; 0o_oooo FLASH_WR_LOCKOUT=writes to flash are enabled ; 00oo CF_IP1=CPU-to-memory clock ratio not 1:1 or 3:2 ; oooo_oooo_oooo reserved ; 00oo CF_IP2=internal address phase wait states ; ; raw=0x00000000. byte-swapped=0x00000000. ; ; Added to use the high drive strength for the memory selects & addressing ;WM32 0xFEC00000 0x70000080 ; select ODCR ;WM8 0xFEE00003 0xff ; low drive for PCI, MEM. high for everything else ; 1 DRV_PCI=medium (50 ohm, not 25) (PMAA2) ; 1 DRV_STD=medium (40 ohm, not 20) ; 1 DRV_MEM_CTRL_1=high (20 ohm data, not 40) (PMAA0) ; 1_ DRV_MEM_CTRL_2=high (20 ohm addr, not 40) (PMAA1) ; 11 DRV_PCI_CLK=high (8 ohms, not 13/20/40) ; 11 DRV_MEM_CLK=high (8 ohms, not 13/20/40) ; ; Added to toggle the DLL_RESET bit WM32 0xFEC00000 0xe0000080 ; select AMBOR ;WM8 0xFEE00000 0xe0 ; DLL_RESET on WM8 0xFEE00000 0x20 ; DLL_RESET on, with 0xFD000000 aliasing disabled WM32 0xFEC00000 0xe0000080 ; select AMBOR ;WM8 0xFEE00000 0xc0 ; DLL_RESET off WM8 0xFEE00000 0x00 ; DLL_RESET off, with FD0 aliasing disabled ; ; define maximal transfer size ;TSZ1 0xFF800000 0xFFFFFFFF ;ROM space (only for PCI boot ROM) ;TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash) TSZ4 0x00000000 0x01FFFFFF ;CS0 - SDRAM TSZ4 0xFF000000 0xFF7FFFFF ;RCS1 - Port X TSZ1 0xFF800000 0xFFFFFFFF ;RCS0 - Flash ROM [TARGET] ; CPUTYPE 8240 ;the CPU type (603EV,750,8240,8260) CPUTYPE 8240 32BIT ;default is 64 bit, which confuses all i/o JTAGCLOCK 0 ;use 16 MHz JTAG clock WORKSPACE 0x00000000 ;workspace in target RAM for fast download 3/8/02 BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint ; VECTOR CATCH ;catch unhandled exceptions ;DCACHE FLUSH ;data cache flushing (FLUSH | NOFLUSH) DCACHE NOFLUSH ;recommended by Abatron if there is no L2 cache [HOST] IP 192.168.3.1 FILE ppcboot.oxc FORMAT BIN LOAD MANUAL ;load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] ; ST m29w800AT on local processor bus (RCS0) ; board has an ST m29w320db installed by mistake 3/8/02 ; ground address A20 and pretend the part is 2M x 8 3/8/02 ; enable flash write in PICR1 (see INIT part) ; set maximal transfer size to 4 bytes (see INIT part) CHIPTYPE AM29BX8 ; Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) ; CHIPSIZE 0x100000 ; The size of one flash chip in bytes (e.g. m29w800AT = 1024 kB) CHIPSIZE 0x200000 ; half of an m29w320db is 2048 kB 3/8/02 BUSWIDTH 8 ; The width of the flash memory bus in bits (8 | 16 | 32 | 64) ; WORKSPACE 0x00000000 ; workspace in SDRAM FILE /tftpboot/telemetry/TLME32.img FORMAT BIN 0xFFF00000 ; sectors 0-22 are not used ; ERASE 0xFFE00000 ; sector 0 ; ERASE 0xFFE02000 ; sector 1 - AMD device only. part of ST sector 0 ; ERASE 0xFFE04000 ; sector 2 ; ERASE 0xFFE06000 ; sector 3 ; ERASE 0xFFE08000 ; sector 4 ; ERASE 0xFFE0A000 ; sector 5 - AMD device only. part of ST sector 4 ; ERASE 0xFFE0C000 ; sector 6 - AMD device only. part of ST sector 4 ; ERASE 0xFFE0E000 ; sector 7 - AMD device only. part of ST sector 4 ; ERASE 0xFFE10000 ; sector 8 ; ERASE 0xFFE20000 ; sector 9 ; ERASE 0xFFE30000 ; sector 10 ; ERASE 0xFFE40000 ; sector 11 ; ERASE 0xFFE50000 ; sector 12 ; ERASE 0xFFE60000 ; sector 13 ; ERASE 0xFFE70000 ; sector 14 ; ERASE 0xFFE80000 ; sector 15 ; ERASE 0xFFE90000 ; sector 16 ; ERASE 0xFFEA0000 ; sector 17 ; ERASE 0xFFEB0000 ; sector 18 ; ERASE 0xFFEC0000 ; sector 19 ; ERASE 0xFFED0000 ; sector 20 ; ERASE 0xFFEE0000 ; sector 21 ; ERASE 0xFFEF0000 ; sector 22 ERASE 0xFFF00000 ;erase sector 23 of flash ERASE 0xFFF10000 ;erase sector 24 of flash ERASE 0xFFF20000 ;erase sector 25 of flash ERASE 0xFFF30000 ;erase sector 26 of flash ERASE 0xFFF40000 ;erase sector 27 of flash ERASE 0xFFF50000 ;erase sector 28 of flash ERASE 0xFFF60000 ;erase sector 29 of flash ERASE 0xFFF70000 ;erase sector 30 of flash ERASE 0xFFF80000 ;erase sector 31 of flash ERASE 0xFFF90000 ;erase sector 32 of flash ERASE 0xFFFA0000 ;erase sector 33 of flash ERASE 0xFFFB0000 ;erase sector 34 of flash ERASE 0xFFFC0000 ;erase sector 35 of flash ERASE 0xFFFD0000 ;erase sector 36 of flash ERASE 0xFFFE0000 ;erase sector 37 of flash ERASE 0xFFFF0000 ;erase sector 38 of flash ; sectors 39-70 are disabled (A20 tied low) [REGS] DMM1 0xFC000000 ;Embedded utility memory base address IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0 IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1 IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2 IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3 FILE reg8240.def