;/****************************************************************************
;*
;* COPYRIGHT (c) Delphi Corporation
;* ALL RIGHTS RESERVED
;*
;*
;* Description: bdi configuration file for the D7860ONSTRS EDU board
;*
;* This configuration file was derived from the Lite5200B
;* Configuration file host-specific modifications are delimited by
;* ### HOST-SPECIFIC MODIFICATIONS START ###
;*                                    and
;* ### HOST-SPECIFIC MODIFICATIONS END   ###
;*  CJC 11/22/2007
;****************************************************************************/
;
[INIT]
; init core register
WREG    MSR             0x00001002  ;MSR  : ME,RI
WM32    0x80000000   0x00008000  ;MBAR : internal registers at 0x80000000
WSPR    311              0x80000000  ;MBAR : save internal register offset
;
; init boot flash for programming : 32 MB
WM32 0x80000004 0x00000000 ; CS0 Start Address
					    ; CS0 start = 0x0000_0000,
WM32 0x80000008 0x000001FF ; CS0 Stop Address
					    ; CS0 stop = 0x01FF_FFFF
WM32 0x80000300 0x00047900 ; Chip Select 0/Boot Configuration Register
					    ; CS0 and CSboot ctrl
					    ; WaitP = 0
					    ; WaitX = 4
					    ; MX - non-multiplexed
					    ; AA - ACK active
					    ; CE - CS enabled
					    ; AS - 24 bits
					    ; DS - 2 bytes
					    ; Bank = 0
					    ; WTyp - WaitP ignored
					    ; WS - no write swap
					    ; RS - no read swap
					    ; WO - write-only disabled
					    ; RO - read-only disabled
; enable flash CSs
WM32 0x80000054 0x00010001 ; IPBI Control Register and Wait State Enable
					    ; CSE - enable CS0, disable CSBOOT
					    ; CS0 Ena - Chip Select 0 Enable
					    ; WSE - Wait State enabled
WM32 0x80000318 0x01000000 ; Chip Select Control Register
					    ; CS Master enable
; init SDRAM CS for 16/8 Micron Type
WM32 0x80000034 0x10000018 ;SDRAM CS0, 32 MByte physical, logical start @ 0x10000000
WM32 0x80000204 0x10000000 ;SDRAM Set tap delay to 0x10
TSZ4  0x10000000 0x11FFFFFF ;SDRAM CS0, 32 MByte
MMAP 0x10000000 0x11FFFFFF ;SDRAM CS0, 32 MByte
; init SDRAM controller for DDR 132MHz, CL=2.5
WM32 0x80000108 0x93733A30 ; SDRAM Config 1
					    ; srd2rwp = 9 ( )
					    ; swt2rwp = 3 ( this is recommended value for DDR )
					    ; rd_latency = 7 ( CAS = 2.5 )
					    ; act2rw = 3 ( suggested value for DDR is 0x2 )
					    ; pre2act = 3 ( recommended value at 132MHz is 0x2 )
					    ; ref2ac = 0xA
					    ; wr_latency = 3
					    ; single read2readwrite delay cl=2.5, swt2rp =3 for DDR, read CAS = 7 (cl=2,5), act2rd= 2,66 -> 3, pre2act=2,66 -> 3, refresh to no read, delay=0xA, Write latency for DDR =3
WM32 0x8000010C 0x45770000 ;SDRAM Config 2
WM32 0x80000104 0xF14F0F00 ;SDRAM Control: Mode register write enablemode reg=0, clk enable=1, DDR mode, auto refresh enabled, hi_addr set, use A10 for precharge, drive rule=1, refresh interval=d15, dqs_oe=b1111
WM32 0x80000104 0xF14F0F02 ;SDRAM Control: Mode register write enable, precharge all
WM32 0x80000100 0x40090000 ;SDRAM Extended Mode DLL enabled, drive strength reduced, QFC disabled
WM32 0x80000100 0x058D0000 ;SDRAM Mode, reset DLLburst 8, sequential, CAS latency
WM32 0x80000104 0xF14F0F02 ;SDRAM Control: precharge all
WM32 0x80000104 0xF14F0F04 ;SDRAM Control: refresh
WM32 0x80000100 0x018D0000 ;SDRAM Mode, normal DLL operation
WM32 0x80000104 0x714F0F00 ;SDRAM Control, lock Mode register
MMAP 0x80000000 0x80003FFF ;Memory map for Internal Register
MMAP 0x80008000 0x8000BFFF ;Memory map for On-chip SRAM
MMAP 0x00000000 0x01FFFFFF ;Memory map for Flash
[TARGET]
CPUTYPE 5200 ;the CPU type
ENDIAN BIG ; default
JTAGCLOCK 0 ;use 16 MHz JTAG clock
BREAK HARD;SOFT or HARD, HARD uses PPC hardware breakpoint
POWERUP 500 ;start delay after power-up detected in ms
BOOTADDR 0x00000100;Boot Low
STARTUP RESET ; startup mode - reset
[HOST]
;* ### HOST-SPECIFIC MODIFICATIONS START ###
IP 10.207.28.32 ;TFTP host IP address
;* ### HOST-SPECIFIC MODIFICATIONS END   ###
LOAD MANUAL ;load code MANUAL or AUTO after reset
DEBUGPORT 2001
PROMPT D7860ONSTRS>
START 0x00000100
TELNET ECHO
[FLASH]
CHIPTYPE MIRRORX16 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE 0x2000000 ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000) 4MB
BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32)
;* ### HOST-SPECIFIC MODIFICATIONS START ###
FILE u-boot.bin ;file must be located in subdirectory of TFTP root directory
FORMAT BIN 0x00000000
;* ### HOST-SPECIFIC MODIFICATIONS END   ###
;Boot Low
ERASE 0x00000000 CHIP ;erase whole chip
;ERASE 0x00000000 ;erase sector of flash
;ERASE 0x00010000 ;erase sector of flash
;ERASE 0x00020000 ;erase sector of flash
;ERASE 0x00030000 ;erase sector of flash
;ERASE 0x00040000 ;erase sector of flash
;ERASE 0x00050000 ;erase sector of flash
;ERASE 0x00060000 ;erase sector of flash
;ERASE 0x00070000 ;erase sector of flash
;ERASE 0x00080000 ;erase sector of flash
;WORKSPACE 0x80008000 ;workspace for faster flashing
[REGS]
FILE        $reg5200.def