;bdiGDB configuration file for MPC8641 ;------------------------------------- ; [INIT] ; init core register #0 WREG MSR 0x00001002 ;MSR : ME,RI #0 WSPR 1008 0x84000000 ;HID0: disable cache, set TBEN bit #0 WSPR 1017 0x00000000 ;L2CR: disable L2 cache ; ;#1 WREG MSR 0x00001002 ;MSR : ME,RI ;#1 WSPR 1008 0x84000000 ;HID0: disable cache, set TBEN bit ; ; Write a valid instruction to vector 0x700 to make SW breakpoints working WM32 0x00000700 0x60000000 ;write NOP instruction WM32 0x00000704 0x4C000064 ;write RFI instruction ;WM32 0x000000f0 0x00000000 ;invalidate page table base [TARGET] CPUTYPE 8641 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock STARTUP RESET ;STARTUP STOP 4000 ;let the boot ROM init the system ;STARTUP HALT ;only core#0 will be handled ; ;STARTUP RUN RUN ;let both core run ;STARTUP HALT HALT ;halt both core at the reset vector ;STARTUP RUN HALT ;STARTUP STOP 4000 HALT ;core#0 runs for 4 second to setup the board ;core#1 will be enabled and halts at reset vector BREAKMODE HARD V ;SOFT or HARD, V forces setting of IABR[TE] STEPMODE HWBP ;TRACE or HWBP, HWBP uses a hardware breakpoint WAKEUP 500 ;support targets that need some wake-up time ;after the BDI releases COP-HRESET. MMU XLAT ;enable address translation PTBASE 0x000000f0 ;POWERUP 3000 ;start delay after power-up detected in ms ;BOOTADDR 0xFEF00100 [HOST] ;IP 151.120.25.119 ;FILE E:\cygwin\home\demo\mpc86xx\fibo.elf ;FORMAT ELF ;FILE 8641_u-boot.bin ;FORMAT BIN 0xFFF00000 ;LOAD MANUAL PROMPT "8641> " [FLASH] CHIPTYPE MIRRORX16 ;Flash is S29GL064M Model R6 CHIPSIZE 0x800000 BUSWIDTH 16 WORKSPACE 0x00002000 ;workspace in SDRAM ;FILE E:\temp\dump512k.bin FILE 8641_u-boot.bin FORMAT BIN 0xfff00000 ERASE 0xfff00000 0x10000 8 ;erase 8 sectors [REGS] FILE $8641_bdi.def