;bdiGDB configuration file for Silicon Tx 8560 ;---------------------------------------- ; ; Use default boot configuration: ; - Boot sequencer disabled ; - Boot from local bus 32-bit ROM ; [INIT] ; init core register ; ; Move the L2SRAM to the initial MMU page WM32 0xFF720000 0x68010000 ;L2CTL WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0 WM32 0xFF720000 0xA8010000 ;L2CTL ; ; load TLB entries, helper code @ 0xfffff000 WM32 0xfffff000 0x7c0007a4 ;tlbwe WM32 0xfffff004 0x7c0004ac ;msync WM32 0xfffff008 0x48000000 ;loop ; ; 1MB TLB1 #15 0x40000000 - 0x400fffff Match u-boot WSPR 624 0x100f0000 ;MAS0: WSPR 625 0x80000500 ;MAS1: WSPR 626 0x4000000a ;MAS2: WSPR 627 0x40000015 ;MAS3: WSPR 628 0x00000000 ;MAS4: EXEC 0xfffff000 ; ; 64 MB TLB1 #2 0xc0000000 - 0xc3ffffff ;WSPR 624 0x10020000 ;MAS0: ;WSPR 625 0x80000800 ;MAS1: ;WSPR 626 0xc0000008 ;MAS2: ;WSPR 627 0xc0000015 ;MAS3: ;EXEC 0xfffff000 ; ; 64 MB TLB1 #3 0x00000000 - 0x03ffffff ;WSPR 624 0x10030000 ;MAS0: ;WSPR 625 0x80000800 ;MAS1: ;WSPR 626 0x00000008 ;MAS2: ;WSPR 627 0x00000015 ;MAS3: ;EXEC 0xfffff000 ; ; 64 MB TLB1 #4 0x04000000 - 0x07ffffff ;WSPR 624 0x10040000 ;MAS0: ;WSPR 625 0x80000800 ;MAS1: ;WSPR 626 0x04000008 ;MAS2: ;WSPR 627 0x04000015 ;MAS3: ;EXEC 0xfffff000 ; ; 16 MB TLB1 #6 0xff000000 - 0xffffffff WSPR 624 0x10060000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xff00000a ;MAS2: WSPR 627 0xff000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff ;WSPR 624 0x10000000 ;MAS0: ;WSPR 625 0x80000700 ;MAS1: ;WSPR 626 0xf0000008 ;MAS2: ;WSPR 627 0xf0000015 ;MAS3: ;EXEC 0xfffff000 ; 256 MB TLB1 #4 0x00000000 - 0x0fffffff Match u-boot WSPR 624 0x10040000 ;MAS0: WSPR 625 0xc0000900 ;MAS1: WSPR 626 0x00000008 ;MAS2: WSPR 627 0x00000015 ;MAS3: EXEC 0xfffff000 ; 256 MB TLB1 #5 0x10000000 - 0x1fffffff Match u-boot WSPR 624 0x10050000 ;MAS0: WSPR 625 0xc0000900 ;MAS1: WSPR 626 0x10000000 ;MAS2: WSPR 627 0x10000015 ;MAS3: EXEC 0xfffff000 ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x20000000 ;L2CTL ; ; Move CCSRBAR to 0x40000000 WM32 0xff700000 0x00040000 ;CCSRBAR to 0x40000000 ; ; Initialize LAWBAR's WM32 0x40000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0x40000C10 0x80f0001d ;LAWAR0 : DDR/SDRAM 1GB WM32 0x40000C28 0x000c0000 ;LAWBAR1 : @0xc0000000 WM32 0x40000C30 0x8040001d ;LAWAR1 : Local Bus 1GB ; ; Setup DDR socket 1 WM32 0x40002000 0x00000007 ;CS0_BNDS WM32 0x40002080 0x80000101 ;CS0_CONFIG WM32 0x40002008 0x0008000f ;CS1_BNDS WM32 0x40002084 0x80000101 ;CS1_CONFIG ; Setup DDR socket 2 WM32 0x40002010 0x00100017 ;CS2_BNDS WM32 0x40002088 0x80000101 ;CS2_CONFIG WM32 0x40002018 0x0018001f ;CS3_BNDS WM32 0x4000208c 0x80000101 ;CS3_CONFIG ; Common DDR set upFixedIntervalTimer WM32 0x40002108 0x36349321 ;TIMING_CFG_1 WM32 0x4000210C 0x00000800 ;TIMING_CFG_2 WM32 0x40002110 0x02000000 ;DDR_SDRAM_CFG WM32 0x40002118 0x00000062 ;DDR_SDRAM_MODE WM32 0x40002124 0x03d00100 ;DDR_SDRAM_IVAL DELAY 200 WM32 0x40002110 0xc2000000 ;DDR_SDRAM_CFG ; ; Setup Flash chip select WM32 0x40005000 0xff001801 ;BR0 WM32 0x40005004 0xff000ff7 ;OR0 ; ; Setup flash programming workspace in L2SRAM ;WM32 0x40020000 0x68010000 ;L2CTL ;WM32 0x40020100 0xf0000000 ;L2SRBAR0 ;WM32 0x40020000 0xA8010000 ;L2CTL ;WSPR 63 0xf0000000 ;IVPR to workspace ;WSPR 415 0x0001500 ;IVOR15 : Debug exception ;WM32 0xf0001500 0x48000000 ;write valid instruction ; ; Setup flash programming workspace in dual port RAM WSPR 63 0x40080000 ;IVPR to workspace WSPR 415 0x000007F0 ;IVOR15 : Debug exception WM32 0x400807F0 0x48000000 ;write valid instruction ; ; Setup for program execution151.120.25.119 ;WM32 0x40020000 0x28010000 ;L2CTL ;WM32 0x40020000 0x28000000 ;L2CTL ;WSPR 63 0x00000000 ;IVPR to workspace ;WSPR 406 0x0000700 ;IVOR6 : Program exception ;WSPR 415 0x0001500 ;IVOR15 : Debug exception ;WM32 0x00000700 0x48000000 ;write valid instruction ;WM32 0x00001500 0x48000000 ;write valid instruction ; [TARGET] CPUTYPE 8560 ;the CPU type ;CPUTYPE 8540 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;JTAGCLOCK 3 ;use 4 MHz JTAG clock BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 200 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms MEMACCESS CORE ;use SAP or CORE for JTAG memory accesses ;MEMACCESS CORE ;use SAP or CORE for JTAG memory accesses ;STARTUP LOOP STARTUP RUN ;SIO 44444 38400 MMU XLAT 0xC0000000 PTBASE 0x000000f0 [HOST] IP 192.168.123.103 ;FILE /GP3/u-boot.bin FILE /GP3/u-boot.ramtest ;FORMAT BIN 0x08f80000 FORMAT BIN 0x04f80000 LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP /GP3/dumpfile [FLASH] CHIPTYPE I28BX16 CHIPSIZE 0x400000 ;The size of one flash chip in bytes BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32) ;WORKSPACE 0x40080000 ;workspace in dual port RAM ;WORKSPACE 0xf0000000 ;workspace in L2SRAM FILE /GP3/u-boot.bin FORMAT BIN 0xFFF80000 ERASE 0xFFF80000 ;erase sector 0 ERASE 0xFFFA0000 ;erase sector 1 ERASE 0xFFFC0000 ERASE 0xFFFE0000 ERASE 0xFFFE4000 ERASE 0xFFFE8000 ERASE 0xFFFEC000 ERASE 0xFFFF0000 ERASE 0xFFFF4000 ERASE 0xFFFF8000 ERASE 0xFFFFC000 [REGS] FILE /GP3/reg8560.def