;
; bdiGDB configuration file for Lifesize Cheetah board
; ----------------------------------------------------
;
[INIT]
; init core register
WREG	MSR             0x00000000      ;clear MSR
WM32	0x000101A8	0xF0000000	;IMMR : internal space
WM32	0xF0010004	0xFFFFFFC3	;SYPCR: disable watchdog
WM32	0xF0010C80	0x00000001	;SCCR : normal operation
WSPR	311		0xF0000000	;MBAR = IMMR
WREG	SRR1		0x00000000	;SRR1 = MSR
WSPR	1008		0xCC88		;HID0
WSPR	1008		0x8088		;HID0

;Disable/invalidate all BAT's
WSPR	528	0
WSPR	529	0
WSPR	530	0
WSPR	531	0
WSPR	532	0
WSPR	533	0
WSPR	534	0
WSPR	535	0
WSPR	536	0
WSPR	537	0
WSPR	538	0
WSPR	539	0
WSPR	540	0
WSPR	541	0
WSPR	542	0
WSPR	543	0

; init DOC/reset area
WM32	0xF0010104	0xFFFF08F6	;OR0: Flash 64K, CS early negate, 6 w.s., Timing relax
WM32	0xF0010100	0xFFF01001	;BR0: Flash @0xFFF00000, 16bit, no parity
WM32	0xF001010C	0xFE002CC0	;OR1  : 32MB, 4 banks, row start at A9, 12 row pins
WM32	0xF0010108	0x00001841	;BR1  : SDRAM @0x00000000, 64bit, no parity

; init SDRAM (PPC bus)
WM16	0xF0010184	0x1900		;MPTPR: Divide Bus clock by 26
WM8	0xF001019C	0x21		;PSRT : Divide MPTPR output by 34

WM32	0xF0010190	0x296AB7A3	;PSDMR: Precharge all banks
WM8	0x00000000	0xFF		;Access SDRAM
WM32	0xF0010190	0x096AB7A3	;PSDMR: CBR Refresh
WM8	0x00000000	0xFF		;Access SDRAM
WM8	0x00000000	0xFF		;Access SDRAM
WM8	0x00000000	0xFF		;Access SDRAM
WM8	0x00000000	0xFF		;Access SDRAM
WM8	0x00000000	0xFF		;Access SDRAM
WM8	0x00000000	0xFF		;Access SDRAM
WM8	0x00000000	0xFF		;Access SDRAM
WM8	0x00000000	0xFF		;Access SDRAM
WM32	0xF0010190	0x196AB7A3	;PSDMR: Mode Set
WM8	0x00000190	0xFF		;Access SDRAM
WM32	0xF0010190	0x416AB7A3	;PSDMR: enable refresh, normal operation

;WM32	0xF0010024	0x00100000	;BCR enable address visibility

; DOC - Lock 
WM32	0xF0010d40	0x00004		;PDIRC - set PORTC.29 (DOC_LOCK) output
WM32	0xF0010d50	0x00004		;PDATC - set PORTC.29 (DOC_LOCK) HI

; M-systems Disc-on-chip setup
RM16	0xFFF01000			; clear anything leftover?
WM16	0xFFF0100c	0x0505		; enter normal mode
WM16	0xFFF01072	0xFAFA		; confirm normal mode
WM16	0xFFF01008	0x0101		; Set big-endian mode
WM16	0xFFF0101a	0x1000		; prepare read chip id[0]
RM16	0xFFF01000			; read chip id[0] (should be 0x0002)
WM16	0xFFF0101a	0x1074		; prepare read chip id[1]
RM16	0xFFF01000			; read chip id[1] (should be 0xFDFF)

[TARGET]
CPUTYPE		8272		;the CPU type (603EV,750,8240,8260)
JTAGCLOCK	4		;use 16 MHz JTAG clock
BOOTADDR	0x100100	;boot address used for start-up break
WORKSPACE	0xF0000000	;workspace in target RAM for fast download
BDIMODE		AGENT		;the BDI working mode (LOADONLY | AGENT | GATEWAY)
STARTUP		RESET
BREAKMODE	HARD		;SOFT or HARD, HARD uses PPC hardware breakpoints
STEPMODE	HWBP		;TRACE or HWBP, HWPB uses a hardware breakpoint
VECTOR		CATCH		;catch unhandled exceptions
DCACHE		NOFLUSH		;data cache flushing (FLUSH | NOFLUSH)
;MMU		XLAT		;translate effective to physical address
POWERUP		3000		;start delay after power-up detected in ms
;REGLIST		SPR		;select register to transfer to GDB
REGLIST		ALL		;select register to transfer to GDB
;VIO		7 9600		;TCP port for virtual IO, BCSR1: enable RS232-1 !!!
;SIO		7 9600		;TCP port for serial IO, check BCSR1: enable RS232-1 !!!

SCANSUCC 1 5 			; Nexperia is the only other device on the JTAG chain

[HOST]
IP		10.10.11.50
FILE		u-boot
FORMAT		ELF
LOAD		MANUAL		;load code MANUAL or AUTO after reset
DEBUGPORT	2001
PROMPT		Lightning4>
DUMP		dump.bin	;Linux: dump.bin must already exist and public writable

[REGS]
DMM1	0xF0000000
FILE	reg8272.def