;bdiGDB configuration file for MicroSys 8240 CU824
;--------------------------------------------------------------
;
[INIT]
; init core register
WREG    MSR             0x00000000      ;clear MSR

; init memory controller (based on DINK32)
WM32    0xFEC00000      0x80000080      ;select MSAR1
WM32    0xFEE00000      0x00ffffff      ;
WM32    0xFEC00000      0x84000080      ;select MSAR2
WM32    0xFEE00000      0xFFFFFFFF      ;
WM32    0xFEC00000      0x90000080      ;select MEAR1
WM32    0xFEE00000      0x1FFFFFFF      ;
WM32    0xFEC00000      0x94000080      ;select MEAR2
WM32    0xFEE00000      0xFFFFFFFF      ;

WM32    0xFEC00000      0x88000080      ;select XMSAR1
WM32    0xFEE00000      0x00030303      ;
WM32    0xFEC00000      0x8C000080      ;select XMSAR2
WM32    0xFEE00000      0x00030303      ;
WM32    0xFEC00000      0x98000080      ;select XMEAR1
WM32    0xFEE00000      0x00030303      ;
WM32    0xFEC00000      0x9C000080      ;select XMEAR2
WM32    0xFEE00000      0x00030303      ;

WM32    0xFEC00000      0xa0000080      ;select MBEN
WM8     0xFEE00000      0x01            ;
WM32    0xFEC00000      0xa0000080      ;select MPM
WM8     0xFEE00003      0x00            ;
WM32    0xFEC00000      0xf0000080      ;select MCCR1
WM32    0xFEE00000      0x0000c803      ;do not set MEMGO
WM32    0xFEC00000      0xf4000080      ;select MCCR2
WM32    0xFEE00000      0xB8060000      ;
WM32    0xFEC00000      0xf8000080      ;select MCCR3
WM32    0xFEE00000      0x00003002      ;
WM32    0xFEC00000      0xfc000080      ;select MCCR4
WM32    0xFEE00000      0x23223025      ;
WM32    0xFEC00000      0xf0000080      ;select MCCR1
WM32    0xFEE00000      0x0008c803      ;now set MEMGO
;
WM32    0xFEC00000      0x78000080      ;select EUMBBAR
WM32    0xFEE00000      0x0000E0FC      ;Embedded utility memory block at 0xFC000000
;
WM32    0xFEC00000      0xa8000080      ;select PICR1
WM32    0xFEE00000      0xC81C04FF      ;enable flash write (Flash on processor bus)

WM8     0xFE800013      0x06            ;enable flash write 
;
; define maximal transfer size
;TSZ1    0xFF800000      0xFFFFFFFF      ;ROM space (only for PCI boot ROM)
TSZ4    0xFF800000      0xFFFFFFFF      ;ROM space (only for Local bus flash)


[TARGET]
CPUTYPE     8240        ;the CPU type (603EV,750,8240,8260)
JTAGCLOCK   1           ;use 16 MHz JTAG clock
;WORKSPACE   0x00000000  ;workspace in target RAM for fast download
BDIMODE     AGENT     	;the BDI working mode (LOADONLY | AGENT | GATEWAY)
BREAKMODE   HARD      	;SOFT or HARD, HARD uses PPC hardware breakpoint
; VECTOR      CATCH       ;catch unhandled exceptions
DCACHE      NOFLUSH	;data cache flushing (FLUSH | NOFLUSH)

[HOST]
IP          192.168.3.1
FILE        /tftpboot/CU824/ppcboot.bin
FORMAT      BIN
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
DEBUGPORT   2001

[FLASH]
; Am29LV800BB on local processor bus (RCS0)
; set PPMC8240 switch SW2-1 OFF => ROM on Local bus
; enable flash write in PICR1 (see INIT part)
; set maximal transfer size to 4 bytes (see INIT part)
CHIPTYPE    I28BX16     ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE    0x200000    ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000)
BUSWIDTH    64          ;The width of the flash memory bus in bits (8 | 16 | 32 | 64)
;WORKSPACE   0x00000000  ;workspace in SDRAM
FILE        /tftpboot/CU824/ppcboot.bin
ERASE	0xFFF00000
ERASE	0xFFF40000
ERASE	0xFFF80000
ERASE	0xFFFC0000

[REGS]
DMM1        0xFC000000                  ;Embedded utility memory base address
IMM1        0xFEC00000  0xFEE00000      ;configuration registers at byte offset 0
IMM2        0xFEC00000  0xFEE00001      ;configuration registers at byte offset 1
IMM3        0xFEC00000  0xFEE00002      ;configuration registers at byte offset 2
IMM4        0xFEC00000  0xFEE00003      ;configuration registers at byte offset 3
FILE        /tftpboot/reg8240.def