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; bdiGDB configuration file for NEXTREAM DMC 405GP Board
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[INIT]
; init core register
WSPR    0x3BA   0x00000000  ;DCWR: Disable data cache write-thru
WSPR    0x3FA   0x00000000      ;DCCR: Disable data cache
WSPR    0x3FB   0x00000000      ;ICCR: Disable instruction cache
WSPR    0x3D6   0x00000000      ;EVPR: Exception Vector Table @0x00000000

; Setup Peripheral Bus
WDCR  0x12      0x00000010      ;Select PB0AP
WDCR  0x13      0x03000480      ;PB0AP: Flash
WDCR  0x12      0x00000000      ;Select PB0CR
WDCR  0x13      0xFE0BA000      ;PB0CR: 8MB at 0xFF800000, r/w, 16bit
WDCR  0x12      0x00000011      ;Select PB1AP
WDCR  0x13      0x00000380      ;PB1AP: NVRAM, REGISTERS and SERVICE BUS
WDCR  0x12      0x00000001      ;Select PB1CR
WDCR  0x13      0xF0058000      ;PB1CR: 4MB at 0xF0000000, r/w, 8bit
;WDCR  0x12     0x00000012      ;Select PB2AP
;WDCR  0x13     0x04815A80      ;PB2AP: Keyboard and Mouse
;WDCR  0x12     0x00000002      ;Select PB2CR
;WDCR  0x13     0xF0118000      ;PB2CR: 1MB at 0xF0100000, r/w, 8bit
;WDCR  0x12     0x00000013      ;Select PB3AP
;WDCR  0x13     0x01815280      ;PB3AP: IRDA
;WDCR  0x12     0x00000003      ;Select PB3CR
;WDCR  0x13     0xF0218000      ;PB3CR: 1MB at 0xF0200000, r/w, 8bit
;WDCR  0x12     0x00000017      ;Select PB7AP
;WDCR  0x13     0x01815280      ;PB7AP: FPGA
;WDCR  0x12     0x00000007      ;Select PB7CR
;WDCR  0x13     0xF0318000      ;PB7CR: 1MB at 0xF0300000, r/w, 8bit

; Setup SDRAM Controller
WDCR  0x10      0x00000080      ;Select SDTR1
WDCR  0x11      0x008a400d      ;SDTR1: SDRAM Timing Register
WDCR  0x10      0x00000040      ;Select MB0CF
WDCR  0x11      0x00062001      ;MB0CF: 32MB @ 0x00000000
;WDCR  0x10     0x00000044      ;Select MB2CF
;WDCR  0x11     0x02062001      ;MB2CF: 32MB @ 0x02000000
WDCR  0x10      0x00000030      ;Select RTR
WDCR  0x11      0x06180000      ;RTR: Refresh Timing Register 15,6 µs
WDCR  0x10      0x00000020      ;Select MCOPT1
WDCR  0x11      0x80c00000      ;MCOPT1: Enable SDRAM Controller

; ## Init On-Chip-Memory (SRAM OCM) ##
WDCR 0x18 0x70000000    ;start address of data SRAM OCM
WDCR 0x19 0x80000000    ;enable accès SRAM data OCM
WDCR 0x1a 0x70000000    ;start address of instruction SRAM OCM
WDCR 0x1b 0x80000000    ;enable accès SRAM instruction SRAM OCM


; Setup MMU info
WM32    0x00000080  0x00000000  ;invalidate page table base

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[TARGET]
JTAGCLOCK   0           ;use 16 MHz JTAG clock
CPUTYPE     405 ;the used target CPU type
BDIMODE     AGENT       ;the BDI working mode (LOADONLY | AGENT)
BREAKMODE   SOFT        ;SOFT or HARD, HARD uses PPC HW breakpoint
VECTOR      CATCH       ;catch unhandled exceptions
SCANSUCC 2 20           ; EPLD = 10 et APEX = 10
;SCANSUCC 3 24          ; CDEC specific!!
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[HOST]
IP          192.168.3.1
FILE        /tftpboot/cpci405/ppcboot.bin
FORMAT      ELF
LOAD        MANUAL              ;load code MANUAL or AUTO after reset
DEBUGPORT   2001
PROMPT      dmc405GP>

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[FLASH]
WORKSPACE   0x70000000  ;workspace in target RAM for fast programming algorithm 
CHIPTYPE    AM29BX16       ;Flash type (AM29F AM29BX8 AM29BX16 I28BX8 I28BX16)
CHIPSIZE    0x800000     ;The size of one flash chip in bytes
BUSWIDTH    16           ;The width of the flash memory bus in bits (8/16/32)
;                       ;The file to program into this Flash
FORMAT      ELF
FILE        /home/harnoisa/tftpboot/nextboot/nextboot
;ERASE       0xFF800000 CHIP ;Erase the whole content of this Flash
ERASE       0xFFFB0000 SECTOR ;Erase the sector content of this Flash
ERASE       0xFFFC0000 SECTOR ;Erase the sector content of this Flash
ERASE       0xFFFD0000 SECTOR ;Erase the sector content of this Flash
ERASE       0xFFFE0000 SECTOR ;Erase the sector content of this Flash
ERASE       0xFFFF0000 SECTOR ;Erase the sector content of this Flash
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[REGS]
IDCR1   0x010   0x011   ;MEMCFGADR and MEMCFGDATA
IDCR2   0x012   0x013   ;EBCCFGADR and EBCCFGDATA
IDCR3   0x014   0x015   ;KIAR and KIDR
;FILE    C:\AG\BDI2000\regPPC405GP.def
;FILE    /home/BSP/TOOLS/abatron_BDI2000/regPPC405GP.def
FILE    reg405gp.def