; *-------------------------------------------------------------------------* ; * file bdiimx31sdram.cfg ; * brief JTAG configuration script for Abatron BDI 2000 and the ; * IMX31 card engine. ; * ; * © Copyright 2006, Logic Product Development, Inc. All Rights Reserved. ; * ; * NOTICE: ; * This file contains source code, ideas, techniques, and information ; * (the Information) which are Proprietary and Confidential Information ; * of Logic Product Development, Inc. This Information may not be used ; * by or disclosed to any third party except under written license, and ; * shall be subject to the limitations prescribed under license. ; * ; *-------------------------------------------------------------------------* ; bdiGDB configuration for ARM IMX31 ; -------------------------------------------------- ; [INIT] WCP15 0x4001 0x00f00000 ;CPACC: allow CP10 and CP11 access WCP10 0x00e8 0x40000000 ;FPEXC: enable VFP11 coprocessor WCP15 0x0001 0x00050078 ; CP15 control register WCP15 0x0707 0x00000000 ; CP15 invalidate I&D WCP15 0x0708 0x00000000 ; CP15 invalidate TLB WCP15 0x4A07 0x00000000 ; CP15 clean write buf. WCP15 0x420F 0x40000015 ; CP15 for enabling the pripheral bus WM32 0x53FC0000 0x040 ; setup ipu WM32 0x53F80000 0x074B0B7D ; init_ccm ;WM32 0x53F80004 0xFF871D58 ; 532-133-66.5 Only at 25% CPU duty cycle ;WM32 0x53F80010 0x0033280C WM32 0x53F80004 0xFF871650 ; 399-133-66.5 OK for 100% CPU duty cycle WM32 0x53F80010 0x00331C23 ; ;WM32 0x53F80004 0xFF871D48 ; 208-104-52 ;WM32 0x53F80010 0x04002000 ;WM32 0xb8002050 0x0000dcf6 ; Configure PSRAM on CS5 ;WM32 0xb8002054 0x444a4541 ;WM32 0xb8002058 0x44443302 ;WM32 0xB6000000 0xCAFECAFE WM32 0xb8002000 0x0000CF03 ; Start 16 bit NorFlash Initialization on CS0 WM32 0xb8002004 0xa0330D01 WM32 0xb8002008 0x00220800 WM32 0xb8002040 0x0000DCF6 ; Configure CPLD on CS4 WM32 0xb8002044 0x444A4541 WM32 0xb8002048 0x44443302 ; ; Configure SDRAM ; Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits ; in SW_PAD_CTL registers ; ; SDCLK WM32 0x43FAC26C 0x121A8DA0 ;Clear pad bit 12. Reset value 0x121A9DA0 ; CAS WM32 0x43FAC270 0x12348521 ;Clear pad bit 22. Reset value 0x12748521 ; RAS WM32 0x43FAC274 0x2A328D23 ;Clear pad bit 2. Reset value 0x2A328D27 ; CS2 (CSD0) WM32 0x43FAC27C 0x12349CA3 ;Clear pad bit 22. Reset value 0x12749CA3 ; DQM3 WM32 0x43FAC284 0x12328DA3 ;Clear pad bit 22. Reset value 0x12728DA3 ; DQM2, DQM1, DQM0 WM32 0x43FAC288 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD31-SD29 WM32 0x43FAC28C 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD28-SD26 WM32 0x43FAC290 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD25-SD23 WM32 0x43FAC294 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD22-SD20 WM32 0x43FAC298 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD19-SD17 WM32 0x43FAC29C 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD16-SD14 WM32 0x43FAC2A0 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD13-SD11 WM32 0x43FAC2A4 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD10-SD8 WM32 0x43FAC2A8 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD7-SD5 WM32 0x43FAC2AC 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD4-SD2 WM32 0x43FAC2B0 0x12348D23 ;Clear pad bit 2,12,22. Reset value 0x12749D27 ; SD1-SD0 WM32 0x43FAC2B4 0x0A148D23 ;Clear pad bit 2,12. Reset value 0x0A149D27 ; A25-A24 WM32 0x43FAC2B8 0x0A328CA1 ;Clear pad bit 12, 22. Reset value 0x0A729CA1 ; A23-A21 WM32 0x43FAC2BC 0x0A328CA3 ;Clear pad bit 2, 12, 22. Reset value 0x0A729CA7 ; A20-A18 WM32 0x43FAC2C0 0x0A328CA3 ;Clear pad bit 2, 12, 22. Reset value 0x0A729CA7 ; A17-A15 WM32 0x43FAC2C4 0x0A328CA3 ;Clear pad bit 2, 12, 22. Reset value 0x0A729CA7 ; A14-A12 WM32 0x43FAC2C8 0x0A328CA3 ;Clear pad bit 2, 12, 22. Reset value 0x0A729CA7 ; A11-A10, MA10 WM32 0x43FAC2CC 0x0A328CA3 ;Clear pad bit 2, 12, 22. Reset value 0x0A729CA7 ; A9-A7 WM32 0x43FAC2D0 0x0A328CA3 ;Clear pad bit 2, 12, 22. Reset value 0x0A729CA7 ; A6-A4 WM32 0x43FAC2D4 0x0A328CA3 ;Clear pad bit 2, 12, 22. Reset value 0x0A729CA7 ; A3-A1 WM32 0x43FAC2D8 0x0A328CA3 ;Clear pad bit 2, 12, 22. Reset value 0x0A729CA7 ; A0 WM32 0x43FAC2DC 0x0A0280A3 ;Clear pad bit 2. Reset value 0x0A0280A7 ; ; Configure enhanced SDRAM/DDR contoller (ESDCTL) ; ; Configure SDRAM timing parameters WM32 0xB8001004 0x006AC73A ;Write to ESDCFG0 reg ; Reset WM32 0xB8001010 0x00000002 ;Write to ESDMISC reg ; Configure for DDR WM32 0xB8001010 0x00000004 ;Write to ESDMISC reg ; Hold for more than 200ns DELAY 1 ;Stall for 1ms ; Set precharge command ; ; COL - 9 column addresses (1 << 20) = 0x00100000 ; ROW - 13 Row addresses (2 << 24) = 0x02000000 ; SP - User mode access (0 << 27) = 0x00000000 ; SMODE - Precharge command (1 << 28) = 0x10000000 ; SDE - Enable controller (1 << 31) = 0x80000000 ; ------------ ; 0x92100000 WM32 0xB8001000 0x92100000 ;Write to ESDCTL0 reg ; Access SDRAM with A10 high to precharge all banks WM32 0x80000F00 0x00000000 ;Write to CSD0 memory region ; Set autorefresh command ; ; COL - 9 column addresses (1 << 20) = 0x00100000 ; ROW - 13 Row addresses (2 << 24) = 0x02000000 ; SP - User mode access (0 << 27) = 0x00000000 ; SMODE - Autorefresh command (2 << 28) = 0x20000000 ; SDE - Enable controller (1 << 31) = 0x80000000 ; ------------ ; 0xA2100000 WM32 0xB8001000 0xA2100000 ;Write to ESDCTL0 reg ; Use writes to refresh all banks of SDRAM WM32 0x80000000 0x00000000 WM32 0x80000000 0x00000000 ; Set load mode command ; ; COL - 9 column addresses (1 << 20) = 0x00100000 ; ROW - 13 Row addresses (2 << 24) = 0x02000000 ; SP - User mode access (0 << 27) = 0x00000000 ; SMODE - Load mode command (3 << 28) = 0x30000000 ; SDE - Enable controller (1 << 31) = 0x80000000 ; ------------ ; 0xB2100000 WM32 0xB8001000 0xB2100000 ;Write to ESDCTL0 reg ; Use SDRAM write to load SDRAM mode register ; address used for mode, data ignored WM8 0x80000033 0x00000000 ;Write to CSD0 memory region WM8 0x81000000 0x00000000 ;Write to CSD0 memory region ; Set load mode command ; ; PRCT - Precharge timer disabled (0 << 0) = 0x00000000 ; BL - Burst of 8 for SDR/DDR (1 << 7) = 0x00000080 ; FP - No full page mode (0 << 8) = 0x00000000 ; PWDT - Power down timer disabled (0 << 10) = 0x00000000 ; SREFR - 4 rows refreshed each clock (3 << 13) = 0x00006000 ; DSIZ - 32-bit memory width (2 << 16) = 0x00020000 ; COL - 10 column addresses (2 << 20) = 0x00200000 ; ROW - 13 Row addresses (2 << 24) = 0x02000000 ; SP - User mode access (0 << 27) = 0x00000000 ; SMODE - Normal mode command (0 << 28) = 0x00000000 ; SDE - Enable controller (1 << 31) = 0x80000000 ; ------------ ; 0x82226080 WM32 0xB8001000 0x82226080 ;Write to ESDCTL0 reg ; Configure misc SDRAM parameters WM32 0xB8001010 0x0000000C ;Write to ESDMISC reg ; Unlock flash blocks WM16 0xa0000000 0x0060 WM16 0xa0000000 0x00D0 WM16 0xa0002000 0x0060 WM16 0xa0002000 0x00D0 WM16 0xa0004000 0x0060 WM16 0xa0004000 0x00D0 WM16 0xa0006000 0x0060 WM16 0xa0006000 0x00D0 WM16 0xa0008000 0x0060 WM16 0xa0008000 0x00D0 WM16 0xa000a000 0x0060 WM16 0xa000a000 0x00D0 WM16 0xa000c000 0x0060 WM16 0xa000c000 0x00D0 WM16 0xa000e000 0x0060 WM16 0xa000e000 0x00D0 WM16 0xa0010000 0x0060 WM16 0xa0010000 0x00D0 WM16 0xa0020000 0x0060 WM16 0xa0020000 0x00D0 WM16 0xa0030000 0x0060 WM16 0xa0030000 0x00D0 WM16 0xa0040000 0x0060 WM16 0xa0040000 0x00D0 WM16 0xa0050000 0x0060 WM16 0xa0050000 0x00D0 WM16 0xa0060000 0x0060 WM16 0xa0060000 0x00D0 WM16 0xa0070000 0x0060 WM16 0xa0070000 0x00D0 WM16 0xa0080000 0x0060 WM16 0xa0080000 0x00D0 WM16 0xa0090000 0x0060 WM16 0xa0090000 0x00D0 WM16 0xa00a0000 0x0060 WM16 0xa00a0000 0x00D0 WM16 0xa00b0000 0x0060 WM16 0xa00b0000 0x00D0 WM16 0xa00c0000 0x0060 WM16 0xa00c0000 0x00D0 WM16 0xa00d0000 0x0060 WM16 0xa00d0000 0x00D0 WM16 0xa00e0000 0x0060 WM16 0xa00e0000 0x00D0 WM16 0xa00f0000 0x0060 WM16 0xa00f0000 0x00D0 WM16 0xa0000000 0x0050 START 0xA0000000 [TARGET] CPUTYPE ARM1136 CLOCK 1 ;JTAG clock (0=Adaptive,1=16MHz,2=8MHz,3=4MHz) POWERUP 100 ;start delay after power-up detected in ms ;STARTUP RESET WAKEUP 100 ;delay time (ms) after reset deassert ENDIAN LITTLE ;memory model (LITTLE | BIG) VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset BREAKMODE HARD ;SOFT or HARD DCC 7 ;DCC I/O via TCP port 7 SCANPRED 2 9 ;no JTAG devices before the ARM1136 SCANSUCC 1 4 ;the ETMBUF after the ARM1136 core [HOST] ;IP 151.120.25.119 ;FILE E:\cygwin\home\demo\arm11\fibo.x ;FORMAT ELF ;LOAD MANUAL ;load file MANUAL or AUTO after reset PROMPT ARM1136> [FLASH] WORKSPACE 0x1FFFC000 ;Workspace in target RAM for fast programming algorithm CHIPTYPE I28BX16 ;Flash type CHIPSIZE 0x200000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) ;FILE $arm1136.cfg ;FORMAT BIN 0x00010000 [REGS]