;bdiGDB configuration file for IOP480 RDK
; ---------------------------------------
;
[INIT]
; init core register
WSPR	954	0x00000000      ;DCWR: Disable data cache write-thru
WSPR	1018	0x00000000	;DCCR: Disable data cache
WSPR	1019	0x00000000	;ICCR: Disable instruction cache

; init memory controller


[TARGET]
JTAGCLOCK   0                   ;use 16 MHz JTAG clock
CPUTYPE     401 		;the used target CPU type
BDIMODE     AGENT   	        ;the BDI working mode (LOADONLY | AGENT)
BREAKMODE   SOFT      	        ;SOFT or HARD, HARD uses PPC hardware breakpoint
RESET       CHIP                ;the reset type (SYSTEM, CHIP, CORE)
;VECTOR      CATCH               ;catch unhandled exceptions

[HOST]
IP          151.120.25.115
FILE        E:\cygnus\root\usr\demo\iop480\vxworks
FORMAT      ELF
LOAD        MANUAL              ;load code MANUAL or AUTO after reset

[FLASH]


[REGS]
DMM1    0x30000000
FILE    E:\cygnus\root\usr\demo\iop480\reg480.def