;bdiGDB configuration file for IBM 440EP Reference Board ; ------------------------------------------------------ ; ; SDRAM setup based on boot ROM settings ; [INIT] ; Setup TLB WTLB 0xF0000095 0x0F00003F ;Boot Space 256MB WTLB 0x00000094 0x0000003F ;SDRAM 256MB @ 0x00000000 WTLB 0xD0000095 0x0800003F ;Flash/SRAM Space 256MB WTLB 0xC0600095 0x0EF6001B ;Peripheral Page Entry ; ; Setup caches WSPR 0x370 0x00000000 ;INV0 WSPR 0x371 0x00000000 ;INV1 WSPR 0x372 0x00000000 ;INV2 WSPR 0x373 0x00000000 ;INV3 WSPR 0x390 0x00000000 ;DNV0 WSPR 0x391 0x00000000 ;DNV1 WSPR 0x392 0x00000000 ;DNV2 WSPR 0x393 0x00000000 ;DNV3 WSPR 0x398 0x0001f800 ;DVLIM WSPR 0x399 0x0001f800 ;IVLIM ; ; Setup Peripheral Bus WDCR 0x12 0x00000010 ;Select EBC0_B0AP WDCR 0x13 0x03017300 ;B0AP: Flash and SRAM WDCR 0x12 0x00000000 ;Select EBC0_B0CR WDCR 0x13 0xfff18000 ;B0CR: 1MB at 0xFFF00000, r/w, 8bit WDCR 0x12 0x00000014 ;Select EBC0_B4AP WDCR 0x13 0x03814340 ;B4AP: 4MB Flash and 1MB SRAM WDCR 0x12 0x00000004 ;Select EBC0_B4CR WDCR 0x13 0x8787a000 ;B4CR: 8MB at 0x87800000, r/w, 16bit ; ; Setup SDRAM Controller (DDR SDRAM) WDCR 0x10 0x00000082 ;Select SDRAM0_CLKTR WDCR 0x11 0x40000000 ;CLKTR: Advance 90 degrees WDCR 0x10 0x00000080 ;Select SDRAM0_TR0 WDCR 0x11 0xc10e40df ;TR0: WDCR 0x10 0x00000081 ;Select SDRAM0_TR1 WDCR 0x11 0x808000a4 ;TR1: WDCR 0x10 0x00000040 ;Select SDRAM0_B0CR WDCR 0x11 0x00062001 ;B0CR: WDCR 0x10 0x00000030 ;Select SDRAM0_RTR WDCR 0x11 0x07e00000 ;RTR: WDCR 0x10 0x00000020 ;Select SDRAM0_CFG0 WDCR 0x11 0x04000000 ;CFG0: 32bit, PMU disable WDCR 0x11 0x84000000 ;CFG0: enable SDRAM DELAY 100 ; ; Setup default vector table WSPR 0x03f 0x00000000 ;IVPR vector base at 0x00000000 WSPR 0x190 0x00000100 ;IVOR0 Critical Input WSPR 0x191 0x00000200 ;IVOR1 Machine Check WSPR 0x192 0x00000300 ;IVOR2 Data Storage WSPR 0x193 0x00000400 ;IVOR3 Instruction Storage WSPR 0x194 0x00000500 ;IVOR4 External Input WSPR 0x195 0x00000600 ;IVOR5 Alignment WSPR 0x196 0x00000700 ;IVOR6 Program WSPR 0x197 0x00000800 ;IVOR7 Reserved WSPR 0x198 0x00000c00 ;IVOR8 System Call WSPR 0x199 0x00000a00 ;IVOR9 Reserved WSPR 0x19a 0x00001000 ;IVOR10 Decrementer WSPR 0x19b 0x00001010 ;IVOR11 Fixed Interval Timer WSPR 0x19c 0x00001020 ;IVOR12 Watchdog Timer WSPR 0x19d 0x00001100 ;IVOR13 Data TLB Error WSPR 0x19e 0x00001200 ;IVOR14 Instruction TLB Error WSPR 0x19f 0x00000f00 ;IVOR15 Debug ; ; Clear DBCR1 and DBCR2 WSPR 0x135 0x00000000 ;DBCR1 WSPR 0x136 0x00000000 ;DBCR2 ; [TARGET] JTAGCLOCK 0 ;use 16 MHz JTAG clock CPUTYPE 440 ;the used target CPU type SCANMISC 8 ;IR length is 8 bits for 440GX WAKEUP 50 ;wakeup time after reset BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWBP uses one or two hardware breakpoints [HOST] IP 151.120.25.119 FILE E:\cygwin\home\demo\mpc860\fibo.elf FORMAT ELF DUMP E:\temp\dump.bin PROMPT 440EP> [FLASH] [REGS] IDCR1 0x010 0x011 ;SDRAM0_CFGADDR and SDRAM0_CFGDATA IDCR2 0x012 0x013 ;EBC0_CFGADDR and EBC0_CFGDATA IDCR3 0x014 0x015 ;EBM0_CFGADDR and EBM0_CFGDATA IDCR4 0x016 0x017 ;PPM0_CFGADDR and PPM0_CFGDATA IDCR5 0x00C 0x00D ;CPR0_CFGADDR and CPR0_CFGDATA IDCR6 0x00E 0x00F ;SDR0_CFGADDR and SDR0_CFGDATA DMM1 0xC0600000 ;Peripheral (should map to 0_EF60_0000) FILE $reg440gx.def