;bdiGDB configuration file for EP85xxM
;----------------------------------------
;
[INIT]
;
; use the following two lines for STARTUP HALT
WSPR    63              0xffff0000      ;IVPR to boot core
WSPR    415             0x0000f000      ;IVOR15 : Debug exception
;
;================= setup for flash programming ===============
; Move CCSRBAR to 0xe0000000
WM32    0xff700000      0x000e0000      ;CCSRBAR to 0xe0000000
;
; Initialize LAWBAR's
WM32    0xe0000C68      0x000e0000      ;LAWBAR3 : @0xe0000000
WM32    0xe0000C70      0x8040001c      ;LAWAR3  : Local Bus  512MB
;
; Setup Flash chip select (32 MB)
WM32    0xe0005000      0xfe001800      ;BR0
WM32    0xe0005004      0xfe000ef1      ;OR0
WM32    0xe0005000      0xfe001801      ;BR0
;
; Setup BCSR chip select (2 MB)
WM32    0xe0005014      0xffe00ef0      ;OR2
WM32    0xe0005010      0xef001001      ;BR2
WM32    0xe0005014      0xffe00ef1      ;OR2
;
; Clear FLASH write protect
WM8	0xef00000b	0xc0
;================= end flash programming =====================
;
[TARGET]
CPUTYPE     8555        ;the CPU type
JTAGCLOCK   0           ;use 16 MHz JTAG clock
;STARTUP     LOOP        ;use boot loop in L2SRAM
STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   HARD      	;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    JTAG        ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP      500         ;give reset time to complete
POWERUP     2000        ;start delay after power-up detected in ms
MEMACCESS   CORE        ;use SAP or CORE for JTAG memory accesses
;
;
[HOST]
IP          10.0.0.70
FILE        pcb85xxram.ep
FORMAT      SREC
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
PROMPT      ep85xxM_32f>
;
[FLASH]
CHIPTYPE    MIRRORX16
CHIPSIZE    0x00800000	;The size of one flash chip in bytes, 8 MB
BUSWIDTH    32		;The width of the flash memory bus in bits (8 | 16 | 32)
;
FILE        u-boot.bin
FORMAT      BIN 0xFFF80000
ERASE       0xFFF80000
ERASE       0xFFFC0000
;
[REGS]
FILE         defs/reg8560.def