;bdiGDB configuration file for EP8548A
;---------------------------------------------------
;
[INIT]
;
; Errata PCI-Ex 26 workaround
WM32    0xFF70A000      0x0000005C      ;Clear bit 1 & 0 in Link Control & Status Register
WM32    0xFF70A004      0x00000000      ;(PCIconfiguration space register at offset 0x5C)
WM32    0xFF7E0F08      0x00000008      ;Clear bit 30 in the engineering only register
                                        ;(CCSR space register at offset 0xe0f08)
;
; use the following two lines for STARTUP HALT
WSPR    63              0xffff0000      ;IVPR to boot core
WSPR    415             0x0000f000      ;IVOR15 : Debug exception
;
;
;================= howto setup TLB entries ===================
; Move the L2SRAM to the initial MMU page
;WM32    0xFF720E44      0x0000001C      ;L2ERRDIS: disable parity error
;WM32    0xFF720000      0x60010000      ;L2CTL
;WM32    0xFF720100      0x0FFF8000      ;L2SRBAR0: map to 0x0_FFF80000
;WM32    0xFF720000      0xA0010000      ;L2CTL
;
; load and execute some boot code
;WM32    0xfffffffc      0x48000000      ;loop
;EXEC    0xfffffffc
;
; load TLB entries, helper code @ 0xfffff000
;WM32    0xfffff000      0x7c0007a4      ;tlbwe
;WM32    0xfffff004      0x7c0004ac      ;msync
;WM32    0xfffff008      0x48000000      ;loop
;WSPR    628             0x00000000      ;MAS4:
;WSPR    630             0x00000000      ;MAS7:
;
; 64 MB  TLB1 #1 0xe0000000 - 0xe3ffffff
;WSPR    624             0x10010000      ;MAS0:
;WSPR    625             0x80000800      ;MAS1:
;WSPR    626             0xe000000a      ;MAS2:
;WSPR    627             0xe0000015      ;MAS3:
;EXEC    0xfffff000
;
;       ........................
;
; Remove the L2SRAM from the initial MMU page
;WM32	0xFF720000      0x20010000      ;L2CTL
;WM32	0xFF720000      0x20000000      ;L2CTL
;================= end setup TLB entries =====================
;
;
;================= setup for flash programming ===============
; Move CCSRBAR to 0xe0000000
WM32    0xff700000      0x000e0000      ;CCSRBAR to 0xe0000000
;
; Initialize LAWBAR's
WM32    0xe0000C08      0x00000000      ;LAWBAR0 : @0x00000000
WM32    0xe0000C10      0x80f0001b      ;LAWAR0  : DDR/SDRAM  256MB
WM32    0xe0000C28      0x000c0000      ;LAWBAR1 : @0xc0000000
WM32    0xe0000C30      0x8040001d      ;LAWAR1  : Local Bus  1GB
;
; Setup Flash chip select
WM32    0xe0005000      0xff001801      ;BR0
WM32    0xe0005004      0xff006f47      ;OR0
WM32    0xe0005008      0xff001001      ;BR1
WM32    0xe000500C      0xff806e65      ;OR1
;================= end flash programming =====================
;


[TARGET]
CPUTYPE     8548        ;the CPU type
JTAGCLOCK   0           ;use 16 MHz JTAG clock
;STARTUP     STOP 5000   ;let U-boot code setup the system
STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   HARD      	;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP        ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP      500         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms


[HOST]
IP          10.0.0.70
FILE        u-boot.bin
FORMAT      ELF
LOAD        MANUAL              ;load code MANUAL or AUTO after reset
DUMP        dump
PROMPT      ep8548a>


[FLASH]
CHIPTYPE    AM29BX16            ;AM29LV641D
CHIPSIZE    0x800000            ;The size of one flash chip in bytes
BUSWIDTH    32                  ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        u-boot.bin
FORMAT      BIN 0xFFF80000
ERASE       0xFFF80000          ;erase sector 0
ERASE       0xFFFa0000          ;erase sector 1
ERASE       0xFFFc0000          ;erase sector 2
ERASE       0xFFFe0000          ;erase sector 3


[REGS]
FILE        defs/reg8548.def