; bdiGDB configuration file for EP80219 board ; ------------------------------------------- ; [INIT] WCP15 0x2001 0x00000001 ;Disable Write Buffer Coalescing WCP15 0x010F 0x000020C1 ;Enable CP0, CP6, CP7 and CP13 access ; ; Init DRAM WM32 0xffffe508 0xA0000000 ;SDBR: Set SDRAM Base Address WM32 0xffffe50c 0x00000014 ;SBR0: 1 bank 128 MB WM32 0xffffe510 0x00000014 ;SBR1: 1 bank 128 MB WM32 0xffffe504 0x00000000 ;SDCR: 64bit / unbuffered WM32 0xffffe550 0x00000000 ;RFR : Disables Refresh Counter WM32 0xffffe500 0x00000005 ;SDIR: nop WM32 0xffffe500 0x00000004 ;SDIR: precharge-all WM32 0xffffe500 0x00000006 ;SDIR: extended-mode-register-set WM32 0xffffe500 0x00000002 ;SDIR: CAS Latency = 2 WM32 0xffffe500 0x00000004 ;SDIR: precharge-all WM32 0xffffe500 0x00000007 ;SDIR: auto-refresh WM32 0xffffe500 0x00000007 ;SDIR: auto-refresh WM32 0xffffe500 0x00000000 ;SDIR: CAS Latency = 2 WM32 0xffffe500 0x0000000f ;SDIR: normal operation WM32 0xffffe550 0x00000300 ;RFR : Enable Refresh Counter ; [TARGET] CPUTYPE IOP321 ;the target CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock ;DBGHANDLER 0x00000000 ;debug handler base address DBGHANDLER 0xFFFF0800 ;debug handler base address ;DBGHANDLER 0x01FEF800 ;debug handler base address ;DBGHANDLER 0xFE000800 ;debug handler base address ENDIAN LITTLE ;memory model (LITTLE | BIG) BREAKMODE SOFT ;SOFT or HARD ;VECTOR CATCH 0xDE ;trap all vectors VTABLO 0xe59ff018 ;Use fixed vetors "ldr pc, [pc, #18]" VTABHI 0xffffffff ;Do not update relocated vector table [HOST] IP 10.0.0.36 FILE ep80219_RAM.elf FORMAT ELF LOAD MANUAL ;load code code MANUAL or AUTO after reset [FLASH] WORKSPACE 0xa0000000 ;workspace in target RAM for fast programming algorithm CHIPTYPE STRATAX16 ;Flash type CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE ep80219_ROM.bin FORMAT BIN 0x00000000 ERASE 0x00000000 ;erase sector 0 ERASE 0x00020000 ;erase sector 1 ERASE 0x00040000 ;erase sector 2 [REGS] FILE defs/reg80321.def