; bdiGDB configuration file for the EP5200C board
; ----------------------------------------------------------
;
; Notes:                
;
; Used to program the boot flash on the EP5200C (16MB Flash) board with MPC5200 on it running SDRAM at 132MHz.
;
;
; 64MByte on CS0, all 64MByte can be used
;  0MByte on CS1
;
;

[INIT]
; init boot flash for programming
WM32 0x80000004 0x0000FF00 ;CS0 start = 0xFF000000
WM32 0x80000008 0x0000FFFF ;CS0 stop  = 0xFFFFFFFF
WM32 0x80000300 0x00047800 ;CS0 and CSboot ctrl

; enable Local Plus CS
WM32 0x80000054 0x00010001 ;CSE: enable CS0, disable CSBOOT
WM32 0x80000318 0x01000000 ;CS Master enable

; enable SDRAM CS
WM32 0x80000034 0x00000019 ;SDRAM CS0
WM32 0x80000038 0x04000000 ;SDRAM CS1
WM32 0x80000B00 0x80000000 ;GPIO Enable CS1

; init SDRAM controller
WM32 0x80000108 0xD2322800 ;SDRAM Config 1
WM32 0x8000010C 0x8AD70000 ;SDRAM Config 2
WM32 0x80000104 0xD14F0000 ;SDRAM Control
WM32 0x80000104 0xD14F0002 ;SDRAM Control: precharge all
WM32 0x80000104 0xD14F0004 ;SDRAM Control: refresh
WM32 0x80000104 0xD14F0004 ;SDRAM Control: refresh
WM32 0x80000100 0x00CD0000 ;SDRAM Mode
WM32 0x80000104 0x514F0000 ;SDRAM Control: Lock Mode Register

; define maximal transfer size
TSZ4 0x00000000	0x03FFFFFF ;SDRAM CS0
TSZ4 0x80000000 0x80003FFF ;Internal Registers
TSZ4 0x80008000 0x8000BFFF ;On-chip SRAM
TSZ4 0xF0000000 0xF0003FFF ;Moved MBAR after dBug has finished booting
TSZ4 0xF0008000 0xF000BFFF ;Moved MBAR (SRAM) dBug has finished booting
TSZ1 0xFF000000 0xFFFFFFFF ;On board flash 

; define the valid memory map
MMAP 0x00000000	0x03FFFFFF ;SDRAM CS0
MMAP 0x80000000 0x80003FFF ;Memory map for Internal Register
MMAP 0x80008000 0x8000BFFF ;Memory map for On-chip SRAM
MMAP 0xF0000000	0xF0003FFF ;Moved MBAR after dBug has finished booting
MMAP 0xF0008000 0xF000BFFF ;Moved MBAR (SRAM) dBug has finished booting
MMAP 0xFF000000 0xFFFFFFFF ;On board flash

[TARGET]
CPUTYPE     5200           ;the CPU type
JTAGCLOCK   0              ;use 16 MHz JTAG clock
BREAK       HARD           ;SOFT or HARD, HARD uses PPC hardware breakpoint
POWERUP     500            ;start delay after power-up detected in ms

[HOST]
IP          10.0.0.175
LOAD        MANUAL         ;load code MANUAL or AUTO after reset

[FLASH]
CHIPTYPE    AM29F          ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE    0x00800000     ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000)
BUSWIDTH    8              ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        ep5200c_16.bin

FORMAT      BIN 0xFFF00000
ERASE       0xFFF00000     ;erase sector of flash
ERASE       0xFFF10000     ;erase sector of flash
ERASE       0xFFF20000     ;erase sector of flash

WORKSPACE   0x00000000	   ;workspace for faster flashing

[REGS]
FILE 		defs\reg5200.def