;ep440EPX ;--------------- ;written by Steven Blakeslee ; ; [INIT] ; Setup TLB WTLB 0xF000009D 0x1F00003F ;Boot Space 256MB WTLB 0x00000095 0x0000003F ;SDRAM 256MB @ 0x00000000 WTLB 0xE0000025 0x1E00003F ;Registers 16KB WTLB 0xEF000075 0x1EF0003F ;Registers 16MB WTLB 0xE0010025 0x0E00103F ;Registers 16KB WTLB 0xC000009D 0x1C00003F ;CPLD 256MB ; ; Setup caches, don't need WSPR 0x370 0x00000000 ;INV0 WSPR 0x371 0x00000000 ;INV1 WSPR 0x372 0x00000000 ;INV2 WSPR 0x373 0x00000000 ;INV3 WSPR 0x390 0x00000000 ;DNV0 WSPR 0x391 0x00000000 ;DNV1 WSPR 0x392 0x00000000 ;DNV2 WSPR 0x393 0x00000000 ;DNV3 WSPR 0x398 0x0001f800 ;DVLIM WSPR 0x399 0x0001f800 ;IVLIM ; ;clear the esr because of bug WSPR 0x03e 0x00000000 ;ESR ; ;looks like the 440EPX needs this to run from RAM WSPR 0x3b3 0x00306000 ;CCR0 ; ; Setup Peripheral Bus ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;FLASH CS0 32M x 16 WDCR 0x12 0x00000010 ;Select EBC0_B0AP WDCR 0x13 0x03017300 ;B0AP: Flash ;WDCR 0x12 0x00000000 ;Select EBC0_B0CR ;WDCR 0x13 0xfe0ba000 ;B0CR: 32Meg, 16Bit at 0xFE000000 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;BCSR NVRAM CS2 ;WDCR 0x12 0x00000012 ;Select EBC0_B2AP ;WDCR 0x13 0x24814580 ;B2AP: CPLD ;WDCR 0x12 0x00000002 ;Select EBC0_B2CR ;WDCR 0x13 0xc0038000 ;B2CR WM32 0xef600b08 0x50011400 ;Enable CS2,CS4,CS5, PerAddr07,06 pin GPIO0_OSRL WM32 0xef600b10 0x50011400 ;Enable CS2,CS4,CS5, PerAddr07,06 pin GPIO0_TSRL WM32 0xef600b30 0x50000000 ;Enable PerAddr07,06 pin ; ; Setup SDRAM Controller (DDR SDRAM) WDCR 0x10 0x000000e0 ;Select SDR0_DDRDL0 WDCR 0x11 0x00000000 WDCR 0x10 0x00000002 ;Select DDR0_02a WDCR 0x11 0x00000000 WDCR 0x10 0x00000000 ;Select DDR0_00 WDCR 0x11 0x0000190A WDCR 0x10 0x00000001 ;Select DDR0_01 WDCR 0x11 0x01000000 WDCR 0x10 0x00000003 ;Select DDR0_03 WDCR 0x11 0x02030602 WDCR 0x10 0x00000004 ;Select DDR0_04 WDCR 0x11 0x13030300 WDCR 0x10 0x00000005 ;Select DDR0_05 WDCR 0x11 0x0202050E WDCR 0x10 0x00000006 ;Select DDR0_06 WDCR 0x11 0x0104C823 WDCR 0x10 0x00000007 ;Select DDR0_07 WDCR 0x11 0x000D0100 WDCR 0x10 0x00000008 ;Select DDR0_08 WDCR 0x11 0x02360001 WDCR 0x10 0x00000009 ;Select DDR0_09 WDCR 0x11 0x00011D5F WDCR 0x10 0x0000000a ;Select DDR0_10 WDCR 0x11 0x00000300 WDCR 0x10 0x0000000b ;Select DDR0_11 WDCR 0x11 0x0027C800 WDCR 0x10 0x0000000c ;Select DDR0_12 WDCR 0x11 0x00000003 WDCR 0x10 0x0000000e ;Select DDR0_14 WDCR 0x11 0x00000000 WDCR 0x10 0x00000011 ;Select DDR0_17 WDCR 0x11 0x19000000 WDCR 0x10 0x00000012 ;Select DDR0_18 WDCR 0x11 0x19191919 WDCR 0x10 0x00000013 ;Select DDR0_19 WDCR 0x11 0x19191919 WDCR 0x10 0x00000014 ;Select DDR0_20 WDCR 0x11 0x0B0B0B0B WDCR 0x10 0x00000015 ;Select DDR0_21 WDCR 0x11 0x0B0B0B0B WDCR 0x10 0x00000016 ;Select DDR0_22 WDCR 0x11 0x00267F0B WDCR 0x10 0x00000017 ;Select DDR0_23 WDCR 0x11 0x00000000 WDCR 0x10 0x00000018 ;Select DDR0_24 WDCR 0x11 0x01010002 WDCR 0x10 0x0000001a ;Select DDR0_26 WDCR 0x11 0x5B260181 WDCR 0x10 0x0000001b ;Select DDR0_27 WDCR 0x11 0x0000682B WDCR 0x10 0x0000001c ;Select DDR0_28 WDCR 0x11 0x00000000 WDCR 0x10 0x0000001f ;Select DDR0_31 WDCR 0x11 0x00000000 WDCR 0x10 0x0000002a ;Select DDR0_42 WDCR 0x11 0x01000006 WDCR 0x10 0x0000002b ;Select DDR0_43 WDCR 0x11 0x050A0200 WDCR 0x10 0x0000002c ;Select DDR0_44 WDCR 0x11 0x00000002 WDCR 0x10 0x00000002 ;Select DDR0_02b WDCR 0x11 0x00000001 ; ; DELAY 100 ; [TARGET] JTAGCLOCK 0 ;use 16 MHz JTAG clock CPUTYPE 440 ;the used target CPU type SCANMISC 8 0xE0 ;IR length is 8 bits for 440GX WAKEUP 500 ;wakeup time after reset BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWBP uses one or two hardware breakpoints ; [HOST] IP 10.0.0.198 ;Windows host FILE u-boot.mot ;FORMAT BIN 0x200000 FORMAT SREC LOAD MANUAL ;load code MANUAL or AUTO after reset ; ; [REGS] IDCR1 0x010 0x011 ;SDRAM0_CFGADDR and SDRAM0_CFGDATA IDCR2 0x012 0x013 ;EBC0_CFGADDR and EBC0_CFGDATA IDCR3 0x014 0x015 ;EBM0_CFGADDR and EBM0_CFGDATA IDCR4 0x016 0x017 ;PPM0_CFGADDR and PPM0_CFGDATA IDCR5 0x00C 0x00D ;CPR0_CFGADDR and CPR0_CFGDATA IDCR6 0x00E 0x00F ;SDR0_CFGADDR and SDR0_CFGDATA FILE defs/reg440epx.def ;