;ep405 64M sdram ;--------------- ;written by Steven Blakeslee ;based on RISCWatch script written by Don Ferencz ; ; [INIT] ; ; Prepare system for synchronous interrupts / exceptions ;set EVPR.EVP = 0x0000 ; Replace this with exception vector table location!!! WSPR 982 0x00000000 ; ; Setup TCR (Timer Control Register) ;set TCR.WP = 0x0 ; Watchdog period = 2^17 clocks ;set TCR.WRC = 0x0 ; Disable watchdog reset ;set TCR.WIE = 0x0 ; Disable watchdog interrupt ;set TCR.PIE = 0x0 ; Disable PIT interrupt ;set TCR.FP = 0x0 ; FIT period = 2^9 clocks ;set TCR.FIE = 0x0 ; Disable FIT interrupt ;set TCR.ARE = 0x1 ; Enable auto reload WSPR 986 0x00400000 ; ; Set up on-chip memory (OCM) ;set OCM0_DSCNTL.DSEN = 0x0 ; Disable data-side accesses ;set OCM0_DSARC.DSAR = 0x3C ; Data-side address range = 0xF0000000 ;set OCM0_DSCNTL.DSEN = 0x1 ; Enable data-side accesses ;set OCM0_DSCNTL.DOF = 0x1 ; ?? (Set to '1' per doc) ;set OCM0_ISCNTL.ISEN = 0x0 ; Disable instruction-side accesses ;set OCM0_ISARC.ISAR = 0x3C ; Instruction-side address range = 0xF0000000 ;set OCM0_ISCNTL.ISEN = 0x1 ; Enable instruction-side accesses ;set OCM0_ISCNTL.ISTCM = 0x1 ; Instruction-side accesses are 2 cycles WDCR 27 0x40000000 WDCR 26 0xf0000000 WDCR 27 0xc0000000 WDCR 25 0x00000000 WDCR 24 0xf0000000 WDCR 25 0xc0000000 ; ; Set up MSR (Machine State Register) ;set MSR.WE = 0x0 ; Disable wait state ;set MSR.CE = 0x0 ; Disable critical interrupts ;set MSR.EE = 0x0 ; Disable external interrupts ;set MSR.PR = 0x0 ; Processor is supervisor state ;set MSR.ME = 0x0 ; Disable machine checks ;set MSR.DWE = 0x0 ; Disable debug wait enable ;set MSR.DE = 0x0 ; Disable debug interrupts ;set MSR.IR = 0x0 ; Disable instruction address translation ;set MSR.DR = 0x0 ; Disable data address translation WREG MSR 0x00000000 ; ; Set up SDRAM controller ; ; Settings are for an EP405 1.2 with 16MB SDRAM (one bank) ; ; NOTE: Order of configuration is important, this procedure is taken from Ch.15 of the ; 405GP UM. ; Set SDRAM Configuration Register ;set SDRAM0_CFG.DCE = 0x0 ; Disable SDRAM controller ;set SDRAM0_CFG.SRE = 0x0 ; Disable self-refresh ;set SDRAM0_CFG.PME = 0x0 ; Disable power management ;set SDRAM0_CFG.MEMCHK = 0x0 ; Disable ECC ;set SDRAM0_CFG.REGEN = 0x0 ; Disable registered memory ;set SDRAM0_CFG.DRW = 0x0 ; Memory width is 32 bits ;set SDRAM0_CFG.BRPF = 0x1 ; Burst prefetch granularity = 16 bytes ;set SDRAM0_CFG.ECCDD = 0x1 ; Tristate ECC check bit output ;set SDRAM0_CFG.EMDULR = 0x0 ; Tristate MemData0:31 except during write WDCR 16 0x20 WDCR 17 0xc00000 ; ; Set SDRAM Timing Register (Samsung K4S561632B-TC1H) ;set SDRAM0_TR.CASL = 0x1 ; CAS/ latency = 2 cycles ;set SDRAM0_TR.PTA = 0x2 ; Precharge-to-activate min = 3 cycles ;set SDRAM0_TR.CTP = 0x1 ; Read/write Cmd-to-Precharge = 2 cycles ;set SDRAM0_TR.LDF = 0x1 ; Leadoff = 2 cycles ;set SDRAM0_TR.RFTA = 0x3 ; CAS-before-RAS refresh-to-activate = 7 cycles ;set SDRAM0_TR.RCD = 0x1 ; RAS-to-CAS delay = 2 cycles WDCR 16 0x80 WDCR 17 0x89400d ; ; Set SDRAM Refresh Timing Register (Samsung K4S561632B-TC1H) ;set SDRAM0_RTR.IV = 0x060 ; Refresh timing WDCR 16 0x30 WDCR 17 0x3000000 ; ; Set SDRAM Bank 0 Configuration Register (16MB bank) ;set SDRAM0_B0CR.BA = 0x000 ; SDRAM Base address = 0x00000000 ;set SDRAM0_B0CR.SZ = 0x2 ; SDRAM size = 16 MB ;set SDRAM0_B0CR.AM = 0x3 ; Addressing mode = 4 (12 rows x 8 cols x 4 banks) ;set SDRAM0_B0CR.BE = 0x1 ; Bank 0 enabled WDCR 16 0x40 WDCR 17 0x0046001 ; ; Set SDRAM Bank 1 Configuration Register (disabled) ;set SDRAM0_B1CR.BE = 0x0 ; Bank 2 disabled ;WDCR 16 0x44 ;WDCR 17 0x00 ; ; Set SDRAM Bank 2 Configuration Register (disabled) ;set SDRAM0_B2CR.BE = 0x0 ; Bank 2 disabled WDCR 16 0x48 WDCR 17 0x00 ; ; Set SDRAM Bank 3 Configuration Register (disabled) ;set SDRAM0_B3CR.BE = 0x0 ; Bank 2 disabled WDCR 16 0x4C WDCR 17 0x00 ; ; DELAY -- 200 us required; we can only delay in discrete seconds! ;delay 1 ; Enable SDRAM (starts precharge, etc.) ;set SDRAM0_CFG.DCE = 0x1 ; Enable SDRAM controller WDCR 16 0x20 WDCR 17 0x80c00000 ; ; Chip selects for flash on PerCS0. Note the EP405 can support flash on CS7 with a ; BCSR setting, not used here!! ; Settings based on PerClk = 50MHz, Flash access = 70 ns ;set EBC0_B0AP.BME = 0x0 ; Bursting disabled ;set EBC0_B0AP.WT = 0x04 ; Wait states = 4 ;set EBC0_B0AP.CSN = 0x0 ; Chip select 'on' timing ;set EBC0_B0AP.OEN = 0x0 ; Output enable 'on' timing ;set EBC0_B0AP.WBN = 0x0 ; Write byte enable 'on' timing ;set EBC0_B0AP.WBF = 0x0 ; Write byte enable 'off' timing ;set EBC0_B0AP.TH = 0x0 ; Transfer hold ;set EBC0_B0AP.RE = 0x0 ; Disable PerReady ;set EBC0_B0AP.SOR = 0x0 ; SampleOn ready disabled ;set EBC0_B0AP.BEM = 0x0 ; Enable BE for write cycles only ;set EBC0_B0AP.PEN = 0x0 ; Parity disabled WDCR 18 0x10 WDCR 19 0x02000000 ; ;set EBC0_B0CR.BAS = 0xFC0 ; Base address = 0xFC000000 ;set EBC0_B0CR.BS = 0x6 ; Bank size = 64MB ;set EBC0_B0CR.BU = 0x3 ; Bank is R/W ;set EBC0_B0CR.BW = 0x2 ; Bus width = 32 bits WDCR 18 0x00 WDCR 19 0xfc0dc000 ; ; Chip select settings for NVRAM & BCSR's on PerCS4 ;set EBC0_B4AP.BME = 0x0 ; Bursting disabled ;set EBC0_B4AP.WT = 0x08 ; Wait states = 8 ;set EBC0_B4AP.CSN = 0x1 ; Chip select 'on' timing (add 1 clk) ;set EBC0_B4AP.OEN = 0x1 ; Output enable 'on' timing (add 1 clk) ;set EBC0_B4AP.WBN = 0x0 ; Write byte enable 'on' timing ;set EBC0_B4AP.WBF = 0x0 ; Write byte enable 'off' timing ;set EBC0_B4AP.TH = 0x0 ; Transfer hold ;set EBC0_B4AP.RE = 0x0 ; Disable PerReady ;set EBC0_B4AP.SOR = 0x0 ; SampleOn ready disabled ;set EBC0_B4AP.BEM = 0x0 ; Enable BE for write cycles only ;set EBC0_B4AP.PEN = 0x0 ; Parity disabled WDCR 18 0x14 WDCR 19 0x04050000 ; ;set EBC0_B4CR.BAS = 0xF40 ; Base address = 0xF4000000 ;set EBC0_B4CR.BS = 0x2 ; Bank size = 4MB ;set EBC0_B4CR.BU = 0x3 ; Bank is R/W ;set EBC0_B4CR.BW = 0x0 ; Bus width = 8 bits WDCR 18 0x04 WDCR 19 0xf4058000 ; [TARGET] JTAGCLOCK 0 ;use 16 MHz JTAG clock CPUTYPE 405 ;the used target CPU type WORKSPACE 0x00000000 ;workspace in target RAM for fast download BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint VECTOR CATCH ;catch unhandled exceptions ; [HOST] IP 10.0.0.161 ;Windows host FILE PCL4xx103.ep FORMAT SREC LOAD MANUAL ;load code MANUAL or AUTO after reset ; [FLASH] CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) CHIPSIZE 0x80000 ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000) BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32) ; [REGS] IDCR1 0x010 0x011 ;MEMCFGADR and MEMCFGDATA IDCR2 0x012 0x013 ;EBCCFGADR and EBCCFGDATA IDCR3 0x014 0x015 ;KIAR and KIDR FILE reg405gp.def