;ep440 256M ;--------------- ;written by Steven Blakeslee ; ; [INIT] ; Setup TLB WTLB 0xF000009D 0x0F00003F ;Boot Space 256MB WTLB 0x0000009D 0x0000003F ;SDRAM 256MB @ 0x00000000 WTLB 0xE000009D 0x0E00003F ;Registers 256MB WTLB 0x8000009D 0x0800003F ;BCSRs 256MB ; ; Setup caches, don't need WSPR 0x370 0x00000000 ;INV0 WSPR 0x371 0x00000000 ;INV1 WSPR 0x372 0x00000000 ;INV2 WSPR 0x373 0x00000000 ;INV3 WSPR 0x390 0x00000000 ;DNV0 WSPR 0x391 0x00000000 ;DNV1 WSPR 0x392 0x00000000 ;DNV2 WSPR 0x393 0x00000000 ;DNV3 WSPR 0x398 0x0001f800 ;DVLIM WSPR 0x399 0x0001f800 ;IVLIM ; ; Setup Peripheral Bus ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;FLASH CS0 32M x 16 WDCR 0x12 0x00000010 ;Select EBC0_B0AP WDCR 0x13 0x03017300 ;B0AP: Flash WDCR 0x12 0x00000000 ;Select EBC0_B0CR ;WDCR 0x13 0xfc0da000 ;B0CR: 64Meg, 16Bit at 0xFC000000 WDCR 0x13 0xfe0ba000 ;B0CR: 32Meg, 16Bit at 0xFE000000 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;BCSR NVRAM CS2 WDCR 0x12 0x00000012 ;Select EBC0_B2AP WDCR 0x13 0x04814500 ;EBC0_B2AP: BCSR WDCR 0x12 0x00000002 ;Select EBC0_B2CR WDCR 0x13 0x80018000 ;EBC0_B2CR: 1Meg, 16Bit at 0x80000000 ;WM32 0xef600b08 0x50010000 ;Enable CS2, PerAddr07,06 pin GPIO0_OSRL 64Meg FLASH ;WM32 0xef600b10 0x50010000 ;Enable CS2, PerAddr07,06 pin GPIO0_TSRL ;WM32 0xef600b30 0x50000000 ;Enable PerAddr07,06 pin WM32 0xef600b08 0x40010000 ;Enable CS2, PerAddr07 pin GPIO0_OSRL 32Meg FLASH WM32 0xef600b10 0x40010000 ;Enable CS2, PerAddr07 pin GPIO0_TSRL WM32 0xef600b30 0x40000000 ;Enable PerAddr07 pin ;WM32 0xef600b08 0x00010000 ;Enable CS2, pin GPIO0_OSRL 16Meg FLASH ;WM32 0xef600b10 0x00010000 ;Enable CS2, pin GPIO0_TSRL ; ; Setup SDRAM Controller (DDR SDRAM) WDCR 0x10 0x00000082 ;Select SDRAM0_CLKTR WDCR 0x11 0x40000000 ;CLKTR: Advance 90 degrees WDCR 0x10 0x00000080 ;Select SDRAM0_TR0 WDCR 0x11 0x410a4012 ;TR0: WDCR 0x10 0x00000081 ;Select SDRAM0_TR1 WDCR 0x11 0x80800819 ;TR1: WDCR 0x10 0x00000040 ;Select SDRAM0_B0CR WDCR 0x11 0x000a4001 ;B0CR: 128M first bank, start 0x0, 13x10 WDCR 0x10 0x00000044 ;Select SDRAM0_B1CR WDCR 0x11 0x080a4001 ;B1CR: 128M second bank, start 0x08000000, 13x10 WDCR 0x10 0x00000030 ;Select SDRAM0_RTR WDCR 0x11 0x04080000 ;RTR: WDCR 0x10 0x00000020 ;Select SDRAM0_CFG0 WDCR 0x11 0x34000000 ;CFG0: 32bit, PMU disable WDCR 0x11 0x84000000 ;CFG0: enable SDRAM ; DELAY 100 ; ; Clear DBCR1 and DBCR2 WSPR 0x135 0x00000000 ;DBCR1 WSPR 0x136 0x00000000 ;DBCR2 ; ; [TARGET] JTAGCLOCK 0 ;use 16 MHz JTAG clock CPUTYPE 440 ;the used target CPU type SCANMISC 8 0xE0 ;IR length is 8 bits for 440GX WAKEUP 500 ;wakeup time after reset BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWBP uses one or two hardware breakpoints ; [HOST] IP 10.0.0.198 ;Windows host FILE pcb4xx100.ep ;FORMAT BIN 0x200000 FORMAT SREC LOAD MANUAL ;load code MANUAL or AUTO after reset ; ; [REGS] IDCR1 0x010 0x011 ;SDRAM0_CFGADDR and SDRAM0_CFGDATA IDCR2 0x012 0x013 ;EBC0_CFGADDR and EBC0_CFGDATA IDCR3 0x014 0x015 ;EBM0_CFGADDR and EBM0_CFGDATA IDCR4 0x016 0x017 ;PPM0_CFGADDR and PPM0_CFGDATA IDCR5 0x00C 0x00D ;CPR0_CFGADDR and CPR0_CFGDATA IDCR6 0x00E 0x00F ;SDR0_CFGADDR and SDR0_CFGDATA FILE defs/reg440gx.def ;