; bdiGDB configuration file for Raza Alchemy DBAu1250 board
; ----------------------------------------------------

[INIT]
; Little Endian
WM32	0xB1900038	0x00000001	;Little Endian
WCP0    16          0x00000003	; cp0_config	;Set KSEG0 CCA = 3

WCP0    12          0x00000000  ;disable interrupts

;	RCS0:  64MB Spansion S29GL512N11T MirrorBit Flash
WM32	0xB4001000	0x00040043	; mem_stcfg0	;RCS0 Configuration
WM32	0xB4001004	0x066181D7	; mem_sttime0	;RCS0 Timing
WM32	0xB4001008	0x11C03F00	; mem_staddr0	;RCS0 Address

;	RCS2: LAN9211
WM32	0xB4001020	0x862D00C0	; mem_stcfg2	;RCS2 Configuration
WM32	0xB4001024	0x14434C12	; mem_sttime2	;RCS2 Timing
WM32	0xB4001028	0x11803F00	; mem_staddr2	;@ 0x18000000

; Setup Clocks - Core = 492Mhz, System/DDR = 123Mhz, Bus = 61.5Mhz
WM32    0xB1900060  0x00000029  ;41 = 492Mhz CPU Clock
;WM32    0xB1900060  0x00000021  ;41 = 396Mhz CPU Clock
WM32    0xB190003c  0x00000001  ;System Clock = CPU Clock/4, Bus Clock = System Clock/2
WM32    0xB1900064  0x00000008  ;8 = 96Mhz AuxPLL Clock for USB/PCI
;WM32    0xB1900014  0x00000100  ;enable 32Khz clock

delay	10	;delay 10msec

;; Setup DDR, 1 Bank, 128Mbyte 32Mx16 chips
;; Setup from AU1200
;WM32 	0xB4000840	0x109001F4	;SDCONFIGA - Refresh Off, DCLK0 on
;WM32 	0xB4000848	0x800A0000	;SDCONFIGB - DDR Clock = System Bus Clock, Full Drive, BB=1
;WM32 	0xB4000800	0x00242001	;SDMODE0 - CL = 3
;WM32 	0xB4000820 	0x231003E0	;SDADDR0 - 128Mbyte at 0
;WM32 	0xB4000848	0x800A0080	;SDCONFIGB - DDR Clock = System Bus Clock, Full Drive, BA=1
;WM32 	0xB40008C0	0x00000000	;SDPRECMD - Issue Precharge
;WM32	0xB4000880 	0x40000000	;SDWRMD0 - Write to Extended MRS
;WM32 	0xB4000880 	0x00000032	;SDWRMD0 - Write to Normal MRS - BURST 4, CL 3 (mobile doesn't support 2.5)
;WM32 	0xB4000848	0x800A0080	;SDCONFIGB - DDR Clock = System Bus Clock, Full Drive, BA=1
;WM32 	0xB40008C0	0x00000000	;SDPRECMD - Issue Precharge
;WM32 	0xB40008C8	0x00000000	;SDAUTOREF - Issue Autorefresh
;WM32 	0xB40008C8	0x00000000	;SDAUTOREF - Issue Autorefresh
;WM32 	0xB4000880 	0x00000032	;SDWRMD0 - Write to Normal MRS - BURST 4, CL 3 (mobile doesn't support 2.5)
;WM32 	0xB4000840	0x909001F4	;SDCONFIGA - Refresh On, 500 (1F4) x 8ns, 4usec @ 124Mhz
;WM32 	0xB4000848	0x80020000	;SDCONFIGB - DDR Clock = System Bus Clock, Full Drive, BB=0, BA=0

; Setup DDR, 1 Bank, 128Mbyte 32Mx16 chips
; Setup from AU1200
WM32 	0xB4000800	0x00242001	;SDMODE0 - CL = 3
WM32 	0xB4000820 	0x231003E0	;SDADDR0 - 128Mbyte at 0
WM32 	0xB4000840	0x109001F4	;SDCONFIGA - Refresh Off, 500 (1F4) x 8ns, 4usec @ 124Mhz
WM32 	0xB4000848	0x80020000	;SDCONFIGB - DDR Clock = System Bus Clock, Full Drive, BB=0, BA=0
WM32 	0xB40008C0	0x00000000	;SDPRECMD - Issue Precharge
WM32	0xB4000880 	0x40000000	;SDWRMD0 - Write to Extended MRS
WM32 	0xB4000880 	0x00000032	;SDWRMD0 - Write to Normal MRS - BURST 4, CL 3 (mobile doesn't support 2.5)
WM32 	0xB40008C0	0x00000000	;SDPRECMD - Issue Precharge
WM32 	0xB40008C8	0x00000000	;SDAUTOREF - Issue Autorefresh
WM32 	0xB40008C8	0x00000000	;SDAUTOREF - Issue Autorefresh
WM32 	0xB4000840	0x909001F4	;SDCONFIGA - Refresh On, 500 (1F4) x 8ns, 4usec @ 124Mhz

delay	10	;delay 10msec
WM16	0xbf000000	0xffff		;place the flash into read mode

; Invalidate Caches
IVIC    4           128         ;Invalidate IC, 4 way, 128 sets
IVDC    4           128         ;Invalidate DC, 4 way, 128 sets

[TARGET]
JTAGCLOCK       0	          ;use 16 MHz JTAG clock
CPUTYPE     	AU1000 		  ;the used target CPU type
ENDIAN      	LITTLE        ;target is big endian
RESET       	JTAG          ;the reset type (NONE, JTAG, HARD)
BDIMODE     	AGENT   	  ;the BDI working mode (LOADONLY | AGENT)
BREAKMODE   	SOFT          ;SOFT or HARD, HARD uses PPC hardware breakpoints
;STEPMODE    	JTAG          ;JTAG, HWBP or SWBP
VECTOR      	CATCH         ;catch unhandled exceptions
STARTUP			RESET
SCANPRED		1 8

[HOST]
IP			192.168.254.19
FILE       	c:\umon_v1.14\umon_ports\csb750\build_csb750\ramtst.elf
FORMAT		ELF
LOAD		MANUAL				;load code MANUAL or AUTO after reset
PROMPT		CSB750_BDI>
TELNET		NOECHO

[FLASH]
WORKSPACE	0xA0200000
CHIPTYPE	MIRRORX16
CHIPSIZE	0x04000000			;64MB
BUSWIDTH	16
FILE       	c:\umon_v1.14\umon_ports\csb750\build_csb750\boot.bin
FORMAT      BIN 0xbfc00000
ERASE		0xbfc00000
ERASE		0xbfc20000
ERASE		0xbfc40000
ERASE      	0xbfc80000
ERASE      	0xbfcc0000

[REGS]
DMM1	0xB4000000				;memory controller base address
DMM2	0xB0400000				;interrupt controller 0 base address
DMM3	0xB1800000				;interrupt controller 1 base address
FILE	C:\abatron\mips32_new\regau1k.def