; bdiGDB configuration file for Cogent CSB737 SAM9263 Board ; ------------------------------------------------- ; [INIT] WM32 0xFFFFFD44 0x00008000 ;Disable watchdog ;WM32 0xFFFFFD00 0xa500000d ;enable user reset WM32 0xFFFFFD08 0xa5000001 ;enable user reset WCP15 0x010F 0x00002001 ;Enable CP0 and CP13 access delay 10 ; Configure Master clock WM32 0xfffffc20 0x00004001 ;Enable main oscilator DELAY 100 WM32 0xfffffc28 0x2060bf09 ;Set PLLA to 200 MHz DELAY 100 WM32 0xfffffc30 0x00000100 ;Select prescaler DELAY 20 WM32 0xfffffc30 0x00000102 ;Select master clock DELAY 20 ; pcm_pcer: enable all peripheral clocks WM32 0xfffffc10 0x2fbfff9c delay 1 ; assign sdram_cs to cs1, all others to sram ; ccfg_ebi0_csa: cs1 sdram ; ccfg_ebi0_csa: disable databus pullup and bus sharing WM32 0xffffed20 0x00010102 delay 1 ;setup CS0 WM32 0xffffe400 0x02020202 delay 1 WM32 0xffffe404 0x0d0d0d0d delay 1 WM32 0xffffe408 0x00100010 delay 1 WM32 0xffffe40c 0x00041003 delay 1 ;;;setup CS2 ;;WM32 0xffffe420 0x02020202 ;;delay 1 ;;WM32 0xffffe424 0x0d0d0d0d ;;delay 1 ;;WM32 0xffffe428 0x00100010 ;;delay 1 ;;WM32 0xffffe42c 0x00041003 ;;delay 1 ; enable d16-31 on port D to be alternate function a (databus) ; also enable *wait (pd5) and A23-25 (pd12-14) WM32 0xfffff804 0xfffffb63 ; disable D16-31, A23-25 and all alt func delay 1 WM32 0xfffff800 0x0000049c ; enable the rest as GPIO delay 1 WM32 0xfffff870 0xfffffb63 ; enable alternate function A delay 1 WM32 0xfffff814 0xfffff488 ; disable any GPIO pins that need to be inputs delay 1 WM32 0xfffff864 0xffffffff ; enable pull-ups on all Port D pins ;; enable ethernet on Port E ;; ethernet PE23-30 ;WM32 0xfffffA70 0x7f800000 ;delay 1 ;WM32 0xfffffA04 0x7f800000 ;delay 1 ;; Port C: enable Debug UART, LCD and Ethernet CRSDV ;WM32 0xfffff604 0xc20fffff ; GPIO Disable ;delay 1 ;WM32 0xfffff600 0x3df00000 ; GPIO Enable ;delay 1 ;WM32 0xfffff670 0xc000000f ; Peripheral A Enable ;delay 1 ;WM32 0xfffff674 0x020ffff0 ; Peripheral B Enable ;delay 1 ;WM32 0xfffff610 0x00000000 ; Output Enable Register ;delay 1 ;WM32 0xfffff630 0x00000000 ; Set Output Data Register ;delay 1 ;WM32 0xfffff634 0x00000000 ; Clear Output Data Register ;delay 1 ; write sdram configuration register, for cas latency 2, ; ras to cas 2, 32-bit, 4 bank, 9 column, 13 row addresses ;WM32 0xffffe208 0x03116159 ; for use with 64MB RAM WM32 0xffffe208 0xa6339279 ; for use with 64MB RAM delay 1 ; setup sdram - all sdram timing is off mclk ; sdrc_mr: issue nop WM32 0xffffe200 0x00000001 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 10 ; sdrc_mr: issue precharge all WM32 0xffffe200 0x00000002 delay 1 WM32 0x20000000 0 delay 10 ; force 8 refresh cycles ; sdrc_mr: issue refresh WM32 0xffffe200 0x00000004 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 1 WM32 0x20000000 0 delay 10 ; set mrs mode WM32 0xffffe200 0x00000003 delay 1 WM32 0x20000021 0 delay 10 ; now set refresh to the final number of ~15usec WM32 0xffffe204 0x00000100 WM32 0xffffe204 0x00000080 delay 1 WM32 0x20000000 0 delay 10 ; set normal mode WM32 0xffffe200 0x00000000 delay 1 WM32 0x20000000 0 delay 10 [TARGET] CPUTYPE ARM926E CLOCK 2 12 ;JTAG clock : start with 5 kHz then use adaptive RESET HARD ;STARTUP RESET ;VECTOR CATCH 0x1f ;catch D_Abort, P_Abort, SWI, Undef and Reset BREAKMODE HARD ;SOFT or HARD, ARM / Thumb break code ENDIAN LITTLE ;memory model (LITTLE | BIG) [HOST] IP 192.168.254.19 FILE c:\umon_v1.15\umon_ports\csb737\build_CSB737\ramtst.elf FORMAT ELF LOAD MANUAL ;load code MANUAL or AUTO after reset PROMPT CSB737_BDI> TELNET NOECHO [FLASH] ;WORKSPACE 0x00200000 ;workspace in internal RAM for fast programming algorithm WORKSPACE 0x20000000 ;workspace in SDRAM for fast programming algorithm CHIPTYPE MIRRORX16 ;Flash type CHIPSIZE 0x4000000 ;The size of one flash chip in bytes - 64Mbytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) FILE c:\umon_v1.15\umon_ports\csb737\build_CSB737\boot.bin ;FILE d:\tmp\KCI_GreenHills\KCI_CSB737.bin FORMAT BIN 0x10000000 ERASE 0x10000000 ERASE 0x10020000 ERASE 0x10040000 ERASE 0x10080000 [REGS] FILE c:\abatron\new_arm7_9\reg926e.def