; ----------------------------------------------------
; bdiGDB configuration for Cogent CSB733 MX31 board
; ----------------------------------------------------
;

[INIT]

; Disable memory management unit (MMU) and both the
; instruction and data caches
WCP15  0x0001 0x00050078		; CP15 control register
WCP15  0x0707 0x00000000		; CP15 invalidate I&D
WCP15  0x0708 0x00000000		; CP15 invalidate TLB
WCP15  0x4A07 0x00000000		; CP15 clean write buf. 
WCP15  0x420F 0x40000015		; CP15 for enabling the pripheral bus

; Critical Clock Settings
WM32 0x53FC0000 0x00000050		; enable ipu
WM32 0x43F0C010 0x00000515		; RVAL/WVAL for L2 cache memory
WM32 0x53F80000 0x074B0B7B		; setup plls; select 32.768 KHz clk as ref. clk
WM32 0x53F80004 0xFF8713D0		; ARM=400MHz, HCLK=133MHz, IPG=33MHz, HSP(IPU) = 133MHz 
WM32 0x53F80010 0x01AD019D		; setup mpll, PD=0, MFD=429, MFN=413, MFI=5
WM32 0x53F80008 0x49FCFE7F		; UPLL
WM32 0x53F80014 0x040C2403		; UPCTL for USB

WM32 0xB8003000 0x00000040		; M3IF setup

; Initialize 16-bit NorFlash on CS0
WM32 0xB8002000 0x00001E00
WM32 0xB8002004 0x00000501

; Initialize 16-bit Ethernet on CS1
;WM32 0xB8002010 0x23525E80
WM32 0xB8002010 0x0000D843
WM32 0xB8002014 0x10000D01
WM32 0xB8002018 0x00720900

; Initialize 16-bit Ethernet on CS1
;WM32 0xB8002010 0x0000De43
;WM32 0xB8002014 0xfffff531
;WM32 0xB8002018 0xffff0A00

; Setup for 32-bit DDR
WM32 0xB8001010 0x00000004		; enable DDR mode
WM32 0xB8001004 0x006ac73a		; timing config
WM32 0xB8001000 0x92100000		; enable CS0 precharge command
WM32 0x80000400 0x0				; precharge all [dummy] write only addr
WM32 0xB8001000 0xA2100000		; enable CS0 auto-refresh command
; two refresh command dummy write only address matter
WM32 0x80000000 0x0
WM32 0x80000000 0x0
WM32 0xB8001000 0xB2100000		; enable CS0 load mode register command
WM8  0x80000033 0xDA			; dummy write only address matter
WM8  0x81000000 0xFF			; dummy write only address matter
WM32 0xB8001000 0x82226080
WM32 0x80000000 0x00000000

[TARGET]
CPUTYPE		ARM1136
;CLOCK		10		; work fine for bring-up JTAG clock (0=Adaptive,1=16MHz,2=8MHz,3=4MHz, 10=10KHz) 
CLOCK		1		; high speed with Freescale MX31 ADS
;WAKEUP		200		; because of medium rising reset line
RESET		HARD 100	; beause of light capacitive load on reset line
;RESET		HARD 	; beause of light capacitive load on reset line
ENDIAN		LITTLE		; memory model (LITTLE | BIG)
BREAKMODE	HARD		; HARD, ARM / Thumb break code
;VECTOR      CATCH 0x1f		;catch D_Abort, P_Abort, SWI, Undef and Reset
;VECTOR      CATCH 0x00		;do not catch any vector
SCANPRED	2 9		;
SCANSUCC	1 4		; the ETMBUF after the ARM1136 core
;STARTUP 	RUN		; RESET or RUN the ARM 11 core is stop after reset
STARTUP 	RESET		; RESET or RUN the ARM 11 core is stop after reset


[HOST]
IP			192.168.254.19
FILE        c:\umon_v1.14\umon_ports\csb733\build_csb733\ramtst.elf
FORMAT		ELF
LOAD		MANUAL		; load code MANUAL or AUTO after reset
PROMPT		BDI_CSB733>
TELNET		NOECHO

[FLASH]
WORKSPACE	0x80000000
CHIPSIZE	0x4000000
CHIPTYPE	MIRRORX16
BUSWIDTH	16
FILE       	C:\umon_v1.14\umon_ports\csb733\build_csb733\boot.bin
FORMAT     	BIN 0xA0000000
ERASE		0xA0000000 
ERASE		0xA0002000 
ERASE		0xA0004000 
ERASE		0xA0006000 
ERASE		0xA0008000 
ERASE		0xA000C000 
ERASE		0xA0020000 
ERASE		0xA0040000 
ERASE		0xA0060000 

[REGS]
FILE    c:\abatron\arm11\reg1136.def