; bdiGDB configuration file for Cogent CSB655 board
; --------------------------------------------------
;
[INIT]

; Little Endian
;WM32	0xB1900038	0x00000001	;Little Endian

WCP0    12          0x00000000  ;disable interrupts

; Setup Static Bus Controller
;WM32    0xB4001000  0x00000243  ;RCS0 CFG - 28F640, BE, 16-Bit, Type 3 (FLASH)
WM32    0xB4001000  0x00046243  ;RCS0 CFG - 28F640, BE, 16-Bit, Type 3 (FLASH)
WM32	0xB4001004  0x040181D7	;RCS0 Timing
WM32    0xB4001008  0x11f83fe0  ;RCS0 ADD - 8MB @ 0x1f000000
;WM32    0xB4001008  0x11f03fc0  ;RCS0 ADD - 16MB @ 0x1f000000
;WM32    0xB4001008  0x11e03f80  ;RCS0 ADD - 32MB @ 0x1f000000

; Setup Clocks - Core = 396Mhz, System/DDR = 132Mhz, Bus = 66Mhz
WM32    0xB1900060  0x00000021  ;33 = 396Mhz CPU Clock
WM32    0xB190003c  0x00000001  ;System Clock = CPU Clock/3, Bus Clock = System Clock/2
WM32    0xB1900064  0x00000020  ;32 = 384Mhz AuxPLL Clock for USB/PCI
WM32    0xB1900014  0x00000100  ;enable 32Khz clock

delay	10	;delay 10msec

; Enable UART0 TXD
WM32    0xB190002c	0x00000008

delay	10	;delay 10msec

; Setup DDR, 1 Bank, 64Mbyte 16Mx16 chips
WM32 	0xB4000800	0x04276221	;SDMODE0 - DDR, 32-Bit
WM32 	0xB4000820 	0xE21003F0	;SDADDR0 - 64Mbyte at 0
WM32 	0xB4000840	0x901001f4	;SDCONFIGA - Refresh Off, DCLK0 on
;WM32 	0xB4000848	0x00000000	;SDCONFIGB - DDR Clock = 66Mhz, Reduced Drive
WM32 	0xB4000848	0x00008000	;SDCONFIGB - DDR Clock = 132Mhz, Reduced Drive
WM32 	0xB40008C0	0x00000000	;SDPRECMD - Issue Precharge
WM32	0xB4000880 	0x40000000	;SDWRMD0 - Write to Extended MRS
WM32 	0xB4000880 	0x00000063	;SDWRMD0 - Write to Normal MRS
WM32 	0xB40008C0	0x00000000	;SDPRECMD - Issue Precharge
WM32 	0xB40008C8	0x00000000	;SDAUTOREF - Issue Autorefresh
WM32 	0xB40008C8	0x00000000	;SDAUTOREF - Issue Autorefresh
WM32 	0xB4000840	0x981001f4	;SDCONFIGA - Refresh On, 7.5usec @ 133Mhz

delay	10	;delay 10msec
WM16	0xbf000000	0xffff		;place the flash into read mode

; Invalidate Caches
IVIC    4           128         ;Invalidate IC, 4 way, 128 sets
IVDC    4           128         ;Invalidate DC, 4 way, 128 sets



[TARGET]
JTAGCLOCK       1             ;use 16 MHz JTAG clock
CPUTYPE     	AU1000 		  ;the used target CPU type
ENDIAN      	BIG           ;target is big endian
RESET       	JTAG          ;the reset type (NONE, JTAG, HARD)
BDIMODE     	AGENT   	  ;the BDI working mode (LOADONLY | AGENT)
BREAKMODE   	SOFT          ;SOFT or HARD, HARD uses PPC hardware breakpoints
STEPMODE    	JTAG          ;JTAG, HWBP or SWBP
VECTOR      	CATCH         ;catch unhandled exceptions
STARTUP			RESET		1000

[HOST]
IP          	192.168.254.22
FILE        	c:\umon_v1.4\umon_ports\csb655\build_csb655\ramtst.elf
;FILE        	c:\umon_v1.4\umon_ports\csb655_le\build_csb655\ramtst.elf
;FORMAT      	BIN 0xa0400000
FORMAT      	ELF 
LOAD        	MANUAL
PROMPT			CSB655_BDI>

[FLASH]
WORKSPACE   	0xa0400000          ;workspace in target RAM for fast programming algorithm
CHIPTYPE    	STRATAX16           ;Flash type
CHIPSIZE    	0x800000           ;The size of one flash chip in bytes	- 8MB
;CHIPSIZE    	0x1000000           ;The size of one flash chip in bytes -16MB
BUSWIDTH    	16                  ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        	c:\umon_v1.4\umon_ports\csb655\build_csb655\boot.bin
;FILE        	c:\umon_v1.4\umon_ports\csb655_le\build_csb655\boot.bin
FORMAT      	BIN 0xbfc00000
ERASE       	0xbfc00000
ERASE       	0xbfc20000
					 
[REGS]
DMM1			0xB4000000      ;memory controller base address
DMM2			0xB0400000      ;interrupt controller 0 base address
DMM3			0xB1800000      ;interrupt controller 1 base address
FILE			c:\abatron\mips32\regau1k.def