; This configuration uses the monitor to setup the board ; [INIT] ; ; Invalidate Caches ;#0 IVIC ;Invalidate IC ;#0 IVDC ;Invalidate DC ; ; Setup TLB ;#0 WTLB 0xC000000000000600 0x00000017 ;Map 0xc000... -> 0x0000... #0 WCP0 12 0x504000e5 ; enable access to 64-bit segmet #0 WM64 0x8001180080000018 0x0000000000E60001 #0 WM64 0x8001180080000018 0x0000000000E60101 #0 WM64 0x8001180080000008 0x00000000288C848C #0 WM64 0x8001180080000010 0x000000008C60C490 #0 WM64 0x8001180080000028 0x00000000F060F020 #0 WM64 0x8001180080000020 0x0000000000000000 #0 WM64 0x8001180080000030 0x00000000FFFFFFFF #0 WM64 0x8001180080000038 0x0000000000000000 #0 WM64 0x8001180080000040 0x0000000000000000 #0 WM64 0x8001180080000000 0x000000002002088A #0 WM64 0x8001180000000000 0x0000000080bf1f40 ; mio_boot_reg_cfg0 ;Global DCLK Initialization Sequence #0 WM64 0x8001180080000000 0x0000000000018097; CVMX_L2C_CFG, dpres0 = 1, dpres1 = 1 #0 WM64 0x80011800880000c0 0x0000000000000080; CVMX_LMCX_DLL_CTL(ddr_interface_num),dreset = 1 #0 WM64 0x80011800e80000b8 0x0000000000000000;CVMX_LMCX_DCLK_CTL(1)=0 #0 WM64 0x80011800880000a8 0x00000000100d0102; CVMX_LMCX_PLL_CTL(0), reset_n = 0,fasten_n = 1,div_reset = 1,fasten_n = 1; ;rd l2d_bst0 DELAY 10 #0 WM64 0x80011800880000a8 0x00000000140d0102; CVMX_LMCX_PLL_CTL(0),reset_n = 1; ;rd l2d_bst0 DELAY 10 #0 WM64 0x80011800880000a8 0x00000000140d0102; CVMX_LMCX_PLL_CTL(0), div_reset = 0; ;rd l2d_bst0 ;;;;LMC0 configuration;;;;; ;LMC0/LMC1 DRESET Initialization Sequence #0 WM64 0x80011800880000C0 0x0000000000000080;CVMX_LMCX_DLL_CTL(ddr_interface_num), dreset = 1; #0 WM64 0x80011800880000c0 0x00000000000000A0; CVMX_LMCX_DLL_CTL(ddr_interface_num, dll90_ena = 1 ;rd l2d_bst0 DELAY 10 #0 WM64 0x80011800880000f0 0x0000000000000000; CVMX_LMCX_BIST_CTL(ddr_interface_num), start = 0; #0 WM64 0x80011800880000f0 0x0000000000000001; CVMX_LMCX_BIST_CTL(ddr_interface_num), start = 1 #0 WM64 0x80011800880000f0 0x0000000000000000; CVMX_LMCX_BIST_CTL(ddr_interface_num), start = 0; ;rd l2d_bst0 DELAY 10 #0 WM64 0x80011800880000c0 0x0000000000000020; CVMX_LMCX_DLL_CTL(ddr_interface_num), dreset = 0; ;rd l2d_bst0 ;LMC0/LMC1 Initialization Sequence #0 WM64 0x8001180088000090 0x0000000000100200; CVMX_LMCX_CTL1(ddr_interface_num), sil_mode = 1, ecc_adr = 1, sequence = 0 #0 WM64 0x8001180088000000 0x0000000000000001;CVMX_LMCX_MEM_CFG0(ddr_interface_num), init_start = 1 ;rd LMC0_MEM_CFG0; (CVMX_LMCX_MEM_CFG0(ddr_interface_num)); ;DRAM Controller Initialization ;The reference-clock inputs to the LMC (DDR2_REF_CLK_*) should be stable when DCOK asserts (refer to Section 26.3). DDR_CK_* should be stable from that point, which is more than 200 us before software can bring up the main memory DRAM interface. ;The generated DDR_CK_* frequency is four times the DDR2_REF_CLK_* frequency. To initialize the main memory and controller, software must perform the following steps in this order: ;1. Write LMC_CTL with [DRESET] = 1, [PLL_BYPASS] = user_value, and [PLL_DIV2] = user_value. #0 WM64 0x8001180088000010 0x00000000007c820c; LMC_CTL,dic=ctl_dic;qs_dic=ctl_qs_dic;mode128b=ddr_interface_wide,inorder_mrf=0,inorder_mwf = 0 , r2r_slot, rdimm_ena, max_write_batch=0xf, xor_bank=1, ddr__pctl=0, ddr__nctl=0 ;2. Read L2D_BST0 and wait for the result. ;rd L2D_BST0; Read CVMX_L2D_BST0 ;3. Wait 10 us (LMC_CTL[PLL_BYPASS] and LMC_CTL[PLL_DIV2] must not transition after this) DELAY 10; Wait 10 us ;4. Write LMC_DDR2_CTL[QDLL_ENA] = 1. #0 WM64 0x8001180088000018 0x00000000c1040301;CVMX_LMCX_DDR2_CTL(ddr_interface_num),ddr2 = 1,rdqs = 0,dll90_byp = 0,dll90_vlu = 0,qdll_ena = 0,ddr2t,ddr_eof,twr,odt_ena,burst8,bank8,crip_mode = 0,bwcnt = 0,pocas = 0,addlat = 0,qdll_ena = 1 ;rd lmc0_ddr2_ctl; CVMX_LMCX_DDR2_CTL(ddr_interface_num)); DELAY 5; must be 200 dclocks ;5. Read L2D_BST0 and wait for the result. ;rd L2D_BST0; Read CVMX_L2D_BST0 ;6. Wait 10 us (LMC_DDR2_CTL[QDLL_ENA] must not transition after this) DELAY 10; Wait 10 us ;7. Write LMC_CTL[DRESET] = 0 (at this point, the DCLK is running and the memory controller is out of reset) ;Configure ODT #0 WM64 0x8001180088000030 0x0000000000000101; CVMX_LMCX_WODT_CTL0(ddr_interface_num) #0 WM64 0x8001180088000078 0x0000000000000011; CVMX_LMCX_RODT_CTL(ddr_interface_num) #0 WM64 0x8001180088000018 0x00000000c1040201;CVMX_LMCX_DDR2_CTL(ddr_interface_num) #0 WM64 0x8001180088000088 0x0000000000001807; CVMX_LMCX_DELAY_CFG(ddr_interface_num) #0 WM64 0x8001180088000008 0x000000003ad6c6af; CVMX_LMCX_MEM_CFG1(ddr_interface_num) #0 WM64 0x8001180088000028 0x00000000f000f000; CVMX_LMCX_COMP_CTL(ddr_interface_num) ;Finally, software must write the LMC_MEM_CFG0 register with LMC_MEM_CFG0[INIT_START] = 1. At that point, CN31XX hardware initiates the standard DDR2 initialization sequence shown in Figure 2. #0 WM64 0x8001180088000000 0x0000000000000000;CVMX_LMCX_MEM_CFG0(ddr_interface_num) ;Reset one shot #0 WM64 0x80011800880000a0 0x0000000000010207; CVMX_LMCX_RODT_COMP_CTL(ddr_interface_num) #0 WM64 0x8001180088000000 0x0000000020000a8a;CVMX_LMCX_MEM_CFG0(ddr_interface_num), ecc_ena,row_lsb,bunk_ena,pbank_lsb,ref_int,tcl = 0,intr_sec_ena = 0,intr_ded_ena = 0,sec_err = ~0,ded_err = ~0,reset = 0; ;rd LMC0_MEM_CFG0; (CVMX_LMCX_MEM_CFG0(ddr_interface_num)); #0 WM64 0x8001180088000000 0x0000000020000a8b;CVMX_LMCX_MEM_CFG0(ddr_interface_num), init_start = 1 ;rd LMC0_MEM_CFG0; (CVMX_LMCX_MEM_CFG0(ddr_interface_num)); #0 WM64 0x8001180088000100 0x0000001555555555; CVMX_LMCX_READ_LEVEL_RANKX(rankidx, ddr_interface_num) #0 WM64 0x8001180088000108 0x0000001555555555; CVMX_LMCX_READ_LEVEL_RANKX(rankidx, ddr_interface_num) #0 WM64 0x80011800880000C8 0x00000000000000fc;CVMX_LMCX_NXM(ddr_interface_num) ;;;;LMC1 configuration;;;; ;;LMC1 DCLK Offsetting Sequence #0 WM64 0x80011800e80000b8 0x0000000000000020;CVMX_LMCX_DCLK_CTL(1),dclk90_ld = 1 #0 WM64 0x80011800e80000b8 0x0000000000000080; CVMX_LMCX_DCLK_CTL(ddr_interface_num, dclk90_ld = 0, off90_ena = 1; ;rd l2d_bst0 ;LMC0 DRESET Initialization Sequence #0 WM64 0x80011800e80000C0 0x0000000000000080;CVMX_LMCX_DLL_CTL(ddr_interface_num), dreset = 1; #0 WM64 0x80011800e80000c0 0x00000000000000A0; CVMX_LMCX_DLL_CTL(ddr_interface_num, dll90_ena = 1 ;rd l2d_bst0 DELAY 10 #0 WM64 0x80011800e80000f0 0x0000000000000000; CVMX_LMCX_BIST_CTL(ddr_interface_num), start = 0; #0 WM64 0x80011800e80000f0 0x0000000000000001; CVMX_LMCX_BIST_CTL(ddr_interface_num), start = 1 #0 WM64 0x80011800e80000f0 0x0000000000000000; CVMX_LMCX_BIST_CTL(ddr_interface_num), start = 0; ;rd l2d_bst0 DELAY 10 #0 WM64 0x80011800e80000c0 0x0000000000000020; CVMX_LMCX_DLL_CTL(ddr_interface_num), dreset = 0; ;rd l2d_bst0 ;LMC0/LMC1 Initialization Sequence #0 WM64 0x80011800e8000090 0x0000000000100200; CVMX_LMCX_CTL1(ddr_interface_num), sil_mode = 1, ecc_adr = 1, sequence = 0 #0 WM64 0x80011800e8000000 0x0000000000000001;CVMX_LMCX_MEM_CFG0(ddr_interface_num), init_start = 1 ;rd LMC1_MEM_CFG0; (CVMX_LMCX_MEM_CFG0(ddr_interface_num)); ;DRAM Controller Initialization ;The reference-clock inputs to the LMC (DDR2_REF_CLK_*) should be stable when DCOK asserts (refer to Section 26.3). DDR_CK_* should be stable from that point, which is more than 200 us before software can bring up the main memory DRAM interface. ;The generated DDR_CK_* frequency is four times the DDR2_REF_CLK_* frequency. To initialize the main memory and controller, software must perform the following steps in this order: ;1. Write LMC_CTL with [DRESET] = 1, [PLL_BYPASS] = user_value, and [PLL_DIV2] = user_value. #0 WM64 0x80011800e8000010 0x00000000007c820c;CVMX_LMCX_CTL(ddr_interface_num),dic=ctl_dic;qs_dic=ctl_qs_dic;mode128b=ddr_interface_wide,inorder_mrf=0,inorder_mwf = 0 , r2r_slot, rdimm_ena, max_write_batch=0xf, xor_bank=1, ddr__pctl=0, ddr__nctl=0 ;2. Read L2D_BST0 and wait for the result. ;rd L2D_BST0; Read CVMX_L2D_BST0 ;3. Wait 10 us (LMC_CTL[PLL_BYPASS] and LMC_CTL[PLL_DIV2] must not transition after this) DELAY 10; Wait 10 us ;4. Write LMC_DDR2_CTL[QDLL_ENA] = 1. #0 WM64 0x80011800e8000018 0x00000000c1040301;CVMX_LMCX_DDR2_CTL(ddr_interface_num),ddr2 = 1,rdqs = 0,dll90_byp = 0,dll90_vlu = 0,qdll_ena = 0,ddr2t,ddr_eof,twr,odt_ena,burst8,bank8,crip_mode = 0,bwcnt = 0,pocas = 0,addlat = 0,qdll_ena = 1 ;rd lmc0_ddr2_ctl; CVMX_LMCX_DDR2_CTL(ddr_interface_num)); DELAY 5; must be 200 dclocks ;5. Read L2D_BST0 and wait for the result. ;rd L2D_BST0; Read CVMX_L2D_BST0 ;6. Wait 10 us (LMC_DDR2_CTL[QDLL_ENA] must not transition after this) DELAY 10; Wait 10 us ;7. Write LMC_CTL[DRESET] = 0 (at this point, the DCLK is running and the memory controller is out of reset) ;Configure ODT #0 WM64 0x80011800e8000030 0x0000000000000101; CVMX_LMCX_WODT_CTL0(ddr_interface_num) #0 WM64 0x80011800e8000078 0x0000000000000011; CVMX_LMCX_RODT_CTL(ddr_interface_num) #0 WM64 0x80011800e8000018 0x00000000c1040201;CVMX_LMCX_DDR2_CTL(ddr_interface_num) #0 WM64 0x80011800e8000088 0x0000000000001807; CVMX_LMCX_DELAY_CFG(ddr_interface_num) #0 WM64 0x80011800e8000008 0x000000003ad6c6af; CVMX_LMCX_MEM_CFG1(ddr_interface_num) #0 WM64 0x80011800e8000028 0x00000000f000f000; CVMX_LMCX_COMP_CTL(ddr_interface_num) ;Finally, software must write the LMC_MEM_CFG0 register with LMC_MEM_CFG0[INIT_START] = 1. At that point, CN31XX hardware initiates the standard DDR2 initialization sequence shown in Figure 2. #0 WM64 0x80011800e8000000 0x0000000000000000;CVMX_LMCX_MEM_CFG0(ddr_interface_num) ;Reset one shot #0 WM64 0x80011800e80000a0 0x0000000000010207; CVMX_LMCX_RODT_COMP_CTL(ddr_interface_num) #0 WM64 0x80011800e8000000 0x0000000020000a8a;CVMX_LMCX_MEM_CFG0(ddr_interface_num), ecc_ena,row_lsb,bunk_ena,pbank_lsb,ref_int,tcl = 0,intr_sec_ena = 0,intr_ded_ena = 0,sec_err = ~0,ded_err = ~0,reset = 0; ;rd LMC0_MEM_CFG0; (CVMX_LMCX_MEM_CFG0(ddr_interface_num)); #0 WM64 0x80011800e8000000 0x0000000020000a8b;CVMX_LMCX_MEM_CFG0(ddr_interface_num), init_start = 1 ;rd LMC0_MEM_CFG0; (CVMX_LMCX_MEM_CFG0(ddr_interface_num)); #0 WM64 0x80011800E8000100 0x0000001555555555; CVMX_LMCX_READ_LEVEL_RANKX(rankidx, ddr_interface_num) #0 WM64 0x80011800E8000108 0x0000001555555555; CVMX_LMCX_READ_LEVEL_RANKX(rankidx, ddr_interface_num) #0 WM64 0x80011800E80000C8 0x00000000000000fc;CVMX_LMCX_NXM(ddr_interface_num) [TARGET] ; common parameters POWERUP 2000 ;power-up delay 2 seconds ;JTAGCLOCK 0 ;use 32 MHz JTAG clock ;JTAGCLOCK 1 ;use 16 MHz JTAG clock JTAGCLOCK 2 ;use 11 MHz JTAG clock ; Core#0 parameters (active core after reset) #0 CPUTYPE CNMIPS ;the used target CPU type #0 ENDIAN BIG ;target is big endian #0 JTAGDELAY 5 ;40 TCK's access delay ;#0 STARTUP STOP 5000 ;STOP mode is used to let the monitor init the system #0 STARTUP HALT ;halt at the boot vector ;#0 WORKSPACE 0xA0000080 ;workspace in target RAM for fast download #0 BREAKMODE HARD ;SOFT or HARD #0 SCANPRED 11 55 ;select last core in scan chain #0 SCANSUCC 0 0 ; ; Core#1 parameters ;#1 CPUTYPE CNMIPS ;#1 ENDIAN BIG ;#1 JTAGDELAY 5 ;#1 STARTUP WAIT ;CPU is held in reset ;#1 BREAKMODE HARD ;#1 SCANPRED 14 70 ;#1 SCANSUCC 1 5 ; ;====================================================== [FLASH] CHIPTYPE AM29BX8 BUSWIDTH 8 CHIPSIZE 0x80000 WORKSPACE 0x00000000 [HOST] #0 PROMPT cnMIPS#0> ;#1 PROMPT cnMIPS#1> [REGS] ;#FILE cnmips.def ; Relative to tftpboot location ;FILE cn58xxp1-abatron-csrs.def FILE cn56xxp1-abatron-csrs.def ; Relative to tftpboot location