;bdiGDB configuration file for AMCC 440EPx "Sequoia" Reference Board
; ------------------------------------------------------
;
; SDRAM setup based on boot ROM settings
;
[INIT]
; Setup TLB
WTLB    0xF0000095  0x1F00003F  ;Boot Space 256MB
WTLB    0x00000094  0x0000003F  ;SDRAM 256MB @ 0x00000000
WTLB    0xE0010025  0x0e00103F  ;On-chip SRAM - 16 KB
WTLB    0xEF600025  0x1EF6001B  ;Peripheral Page Entry - 16 KB
;
; Setup caches
WSPR    0x370   0x00000000      ;INV0
WSPR    0x371   0x00000000      ;INV1
WSPR    0x372   0x00000000      ;INV2
WSPR    0x373   0x00000000      ;INV3
WSPR    0x390   0x00000000      ;DNV0
WSPR    0x391   0x00000000      ;DNV1
WSPR    0x392   0x00000000      ;DNV2
WSPR    0x393   0x00000000      ;DNV3
WSPR    0x398   0x0001f800      ;DVLIM
WSPR    0x399   0x0001f800      ;IVLIM
;
; Setup Peripheral Bus
WDCR	0x12	0x00000010	;Select EBC0_B0AP
WDCR	0x13	0x03017300	;B0AP: NOR Flash
WDCR	0x12	0x00000000	;Select EBC0_B0CR
WDCR	0x13	0xfe0ba000	;B0CR: 32MB at 0xFE000000, r/w, 8bit
;
WDCR	0x12	0x00000012	;Select EBC0_B2AP
WDCR	0x13	0x24814580 	;B4AP: CPLD
WDCR	0x12	0x00000002	;Select EBC0_B2CR
WDCR	0x13	0xc0038000 	;B2CR: 2MB at 0xC0000000, r/w, 16bit
;
; Setup On-chip SRAM
WDCR  0x380 0xE0010580	;Setup base address as 0xE0010000, size 16 KB, read/write access
WDCR  0x38A 0x00000000  ;Disable parity checking
;
; Setup SDRAM Controller - skipped because on chip SRAM used for Flash programming

;
; Setup default vector table
WSPR    0x03f   0x00000000      ;IVPR   vector base at 0x00000000
WSPR    0x190   0x00000100      ;IVOR0  Critical Input
WSPR    0x191   0x00000200      ;IVOR1  Machine Check
WSPR    0x192   0x00000300      ;IVOR2  Data Storage
WSPR    0x193   0x00000400      ;IVOR3  Instruction Storage
WSPR    0x194   0x00000500      ;IVOR4  External Input
WSPR    0x195   0x00000600      ;IVOR5  Alignment
WSPR    0x196   0x00000700      ;IVOR6  Program
WSPR    0x197   0x00000800      ;IVOR7  Reserved
WSPR    0x198   0x00000c00      ;IVOR8  System Call
WSPR    0x199   0x00000a00      ;IVOR9  Reserved
WSPR    0x19a   0x00001000      ;IVOR10 Decrementer
WSPR    0x19b   0x00001010      ;IVOR11 Fixed Interval Timer
WSPR    0x19c   0x00001020      ;IVOR12 Watchdog Timer
WSPR    0x19d   0x00001100      ;IVOR13 Data TLB Error
WSPR    0x19e   0x00001200      ;IVOR14 Instruction TLB Error
WSPR    0x19f   0x00000f00      ;IVOR15 Debug
;
; Clear DBCR1 and DBCR2
WSPR    0x135   0x00000000      ;DBCR1
WSPR    0x136   0x00000000      ;DBCR2
;


[TARGET]
JTAGCLOCK   0                   ;use 16 MHz JTAG clock
CPUTYPE     440 		;the used target CPU type
SCANMISC    8                   ;IR length is 8 bits for 440GX/440EP
WAKEUP      50                  ;wakeup time after reset
BREAKMODE   SOFT      	        ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    JTAG                ;JTAG or HWBP, HWBP uses one or two hardware breakpoints


[HOST]
IP          192.168.1.19
FILE        /images/440/sequoia/kdiags.sequoia.standalone.bin
FORMAT      ELF
PROMPT      440EPx>


[FLASH]
; Boot Flash 32MB (S29GL256N) at 0xfe000000
WORKSPACE   0xe0010000  ;workspace in On-Chip RAM
CHIPTYPE    AM29BX16    ;Flash type
CHIPSIZE    0x200000    ;The size of one flash chip in bytes
BUSWIDTH    16          ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        /images/sequoia.uboot.bin
FORMAT      BIN 0xFFF80000
ERASE       0xFFF80000  0x20000 4  ;erase four 128kB sectors
;

[REGS]
IDCR1	0x010	0x011	;SDRAM0_CFGADDR and SDRAM0_CFGDATA
IDCR2	0x012	0x013	;EBC0_CFGADDR   and EBC0_CFGDATA
IDCR3	0x014	0x015	;EBM0_CFGADDR   and EBM0_CFGDATA
IDCR4	0x016	0x017	;PPM0_CFGADDR   and PPM0_CFGDATA
IDCR5	0x00C	0x00D	;CPR0_CFGADDR   and CPR0_CFGDATA
IDCR6	0x00E	0x00F	;SDR0_CFGADDR   and SDR0_CFGDATA
DMM1    0xEF600000      ;Peripheral (should map to 1_EF60_0000)
FILE    $reg440epx.def