;bdiGDB configuration file for AMCC 440SP LUAN 2 Board ; ---------------------------------------------------- ; [INIT] ; Setup TLB WTLB 0xF0000094 0x4F00003F ;Boot Space 256MB (Flash,SRAM,EPLD) ;WTLB 0x00000094 0x0000003F ;SDRAM 256MB @ 0x00000000 ;WTLB 0x10000094 0x0100003F ;SDRAM 256MB @ 0x10000000 ; MMAP 0x000000 0xFFFFFFFF ; LAST 16 MB (RUY) ; Setup caches ;WSPR 0x370 0x00000000 ;INV0 ;WSPR 0x371 0x00000000 ;INV1 ;WSPR 0x372 0x00000000 ;INV2 ;WSPR 0x373 0x00000000 ;INV3 ;WSPR 0x374 0x00000000 ;ITV0 ;WSPR 0x375 0x00000000 ;ITV1 ;WSPR 0x376 0x00000000 ;ITV2 ;WSPR 0x377 0x00000000 ;ITV3 ;WSPR 0x390 0x00000000 ;DNV0 ;WSPR 0x391 0x00000000 ;DNV1 ;WSPR 0x392 0x00000000 ;DNV2 ;WSPR 0x393 0x00000000 ;DNV3 ;WSPR 0x394 0x00000000 ;DTV0 ;WSPR 0x395 0x00000000 ;DTV1 ;WSPR 0x396 0x00000000 ;DTV2 ;WSPR 0x397 0x00000000 ;DTV3 ;WSPR 0x398 0x0001f800 ;DVLIM ;WSPR 0x399 0x0001f800 ;IVLIM ; ; Setup Peripheral Bus - ruy WDCR 0x12 0x00000010 ;Select EBC0_B0AP WDCR 0x13 0x03800000 ;B0AP: Flash, no burst, 7 ws WDCR 0x12 0x00000000 ;Select EBC0_B0CR WDCR 0x13 0xFF09a000 ;B0CR: 16MB at 0xFF000000, r/w, 16bit ;WDCR 0x12 0x00000011 ;Select EBC0_B1AP ;WDCR 0x13 0x02095a40 ;B1AP: EPLD and FRAM ;WDCR 0x12 0x00000001 ;Select EBC0_B1CR ;WDCR 0x13 0xf8018000 ;B1CR: 1MB at 0xF8000000, r/w, 8bit ; ;WDCR 0x12 0x00000012 ;Select EBC0_B2AP ;WDCR 0x13 0x03800000 ;B2AP: 4 MB Flash ;WDCR 0x12 0x00000002 ;Select EBC0_B2CR ;WDCR 0x13 0xff858000 ;B2CR: 4MB at 0xFF800000, r/w, 8bit ; ; Setup DDR2 Controller ;WDCR 0x10 0x00000021 ;Select MCIF0_MCOPT2 ;WDCR 0x11 0x84000000 ;MCOPT2: Clear DCEN BIT ;WDCR 0x10 0x00000020 ;Select MCIF0_MCOPT1 ;WDCR 0x11 0x2D122000 ;MCOPT1: ECC OFF,64 bits,4 banks,DDR2 ;WDCR 0x10 0x00000026 ;Select MCIF0_CODT ;WDCR 0x11 0x00800026 ;CODT: Die Termination On ;WDCR 0x10 0x00000081 ;Select MCIF0_WRDTR ;WDCR 0x11 0x82000800 ;WRDTR: Write DQS Adv 90 + Fractional DQS Delay ;WDCR 0x10 0x00000080 ;Select MCIF0_CLKTR ;WDCR 0x11 0x80000000 ;CLKTR: Adv Addr clock by 180 deg ;WDCR 0x10 0x00000040 ;Select MCIF0_MB0CF ;WDCR 0x11 0x00000201 ;MB0CF: Turn on CS0, N x 10 coll ;WDCR 0x10 0x00000044 ;Select MCIF0_MB1CF ;WDCR 0x11 0x00000201 ;MB1CF: Turn on CS0, N x 10 coll ;WDCR 0x10 0x00000030 ;Select MCIF0_RTR ;WDCR 0x11 0x08200000 ;RTR: Refresh every 7.8125uS ;WDCR 0x10 0x00000085 ;Select MCIF0_SDTR1 ;WDCR 0x11 0x80201000 ;SDTR1: Timing Register 1 ;WDCR 0x10 0x00000086 ;Select MCIF0_SDTR2 ;WDCR 0x11 0x42103242 ;SDTR2: Timing Register 2 ;WDCR 0x10 0x00000087 ;Select MCIF0_SDTR3 ;WDCR 0x11 0x0C100D14 ;SDTR3: Timing Register 3 ;WDCR 0x10 0x00000088 ;Select MCIF0_MMODE ;WDCR 0x11 0x00000642 ;MMODE: CAS = 4 cycles ;WDCR 0x10 0x00000089 ;Select MCIF0_MEMODE ;WDCR 0x11 0x00000400 ;MEMODE: Diff DQS disabled, ODT term disabled ; ;WDCR 0x10 0x00000050 ;Select MCIF0_INITPLR0 ;WDCR 0x11 0x81b80000 ;INITPLR0: NOP ;WDCR 0x10 0x00000051 ;Select MCIF0_INITPLR1 ;WDCR 0x11 0x82100400 ;INITPLR1: PRE ;WDCR 0x10 0x00000052 ;Select MCIF0_INITPLR2 ;WDCR 0x11 0x80820000 ;INITPLR2: EMR2 ;WDCR 0x10 0x00000053 ;Select MCIF0_INITPLR3 ;WDCR 0x11 0x80830000 ;INITPLR3: EMR3 ;WDCR 0x10 0x00000054 ;Select MCIF0_INITPLR4 ;WDCR 0x11 0x80810000 ;INITPLR4: EMR DLL ENABLE ;WDCR 0x10 0x00000055 ;Select MCIF0_INITPLR5 ;WDCR 0x11 0x80800542 ;INITPLR5: MR DLL RESET ;WDCR 0x10 0x00000056 ;Select MCIF0_INITPLR6 ;WDCR 0x11 0x82100400 ;INITPLR6: PRE ;WDCR 0x10 0x00000057 ;Select MCIF0_INITPLR7 ;WDCR 0x11 0x99080000 ;INITPLR7: Refresh ;WDCR 0x10 0x00000058 ;Select MCIF0_INITPLR8 ;WDCR 0x11 0x99080000 ;INITPLR8: Refresh ;WDCR 0x10 0x00000059 ;Select MCIF0_INITPLR9 ;WDCR 0x11 0x99080000 ;INITPLR9: Refresh ;WDCR 0x10 0x0000005A ;Select MCIF0_INITPLR10 ;WDCR 0x11 0x99080000 ;INITPLR10: Refresh ;WDCR 0x10 0x0000005B ;Select MCIF0_INITPLR11 ;WDCR 0x11 0x80800442 ;INITPLR11: MR ;WDCR 0x10 0x0000005C ;Select MCIF0_INITPLR12 ;WDCR 0x11 0x80810380 ;INITPLR12: EMR OCD Default ;WDCR 0x10 0x0000005D ;Select MCIF0_INITPLR13 ;WDCR 0x11 0x80810000 ;INITPLR12: EMR OCD Exit ;DELAY 10 ; ;WDCR 0x10 0x00000021 ;Select MCIF0_MCOPT2 ;WDCR 0x11 0x28000000 ;MCOPT2: Execute Preloaded Initialization Sequence, set DC_EN ;DELAY 100 ; ;WDCR 0x40 0x0000F800 ;MQ0_B0BAS: Base Address 0x00000000 / Size 256 MB ;WDCR 0x41 0x1000F800 ;MQ0_B1BAS: Base Address 0x10000000 / Size 256 MB ; ;WDCR 0x10 0x00000078 ;Select MCIF0_RDCC ;WDCR 0x11 0x00000000 ;RDCC: Auto Set Read Stage ;WDCR 0x10 0x00000070 ;Select MCIF0_RQDC ;WDCR 0x11 0x8000003A ;RQDC: Read DQS Delay Control Enabled + Fractional DQS Delay ;WDCR 0x10 0x00000074 ;Select MCIF0_RFDC ;WDCR 0x11 0x00000200 ;RFDC: 2 clock feedback delay ; ; Trying to setup GPIO's ;WDCR 0X0E 0X4100 ; Access SDR0_PFC0 ;WDCR 0X0F 0X00000004 ; ENABLE GPIO29 -> RS232_EN# ;WDCR 0x4100 0x00000001 ; Enable GPIO31 ;WM32 0x1f000700 0x00000001 ; Output Register set bit to 1 ;WM32 0x1f000704 0x00000001 ; Tri-state disable ;WM32 0x1f000718 0x00000000 ; Open-drain disable [TARGET] JTAGCLOCK 0 ;use 16 MHz JTAG clock CPUTYPE 440 ;the used target CPU type RESET HARD ;hardware reset used on Nimbus SCANMISC 8 ;IR length is 8 bits for 440SP WAKEUP 500 ;wakeup time after reset BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE HWBP ;JTAG or HWBP, HWBP uses one or two hardware breakpoints [HOST] ;IP 192.168.201.132 ;FILE kdiags.bin ; ;FORMAT BIN ;DUMP ; PROMPT NIMBUS_440SPe> [FLASH] ;program large 4MB Flash (AM29LV033C) at 0xff800000 ;WORKSPACE 0xEFFFF000 ;workspace in SRAM for fast programming algorithm CHIPTYPE AM29BX16 ;Flash type CHIPSIZE 0x01000000 ;The size of one flash chip in bytes BUSWIDTH 16 ;The width of the flash memory bus in bits (8 | 16 | 32) ;FILE kdiags_1.bin ;FORMAT BIN 0xFFF00000 ;ERASE 0xFFF00000 0X10000 16 ;erase last 16 sectors [REGS] IDCR1 0x00C 0x00D ;CPR0_CFGADDR and CPR0_CFGDATA IDCR2 0x00E 0x00F ;SDR0_CFGADDR and SDR0_CFGDATA IDCR3 0x010 0x011 ;MCIF0_CFGADDR and MCIF0_CFGDATA IDCR4 0x012 0x013 ;EBC0_CFGADDR and EBC0_CFGDATA FILE $reg440sp.def