;Register definition for MCF5485 ;=============================== ; ; name: user defined name of the register ; type: the type of the register ; DREG data register ; AREG address register ; CREG control register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; ; Additional Control Register ; cacr CREG 0x002 32 asid CREG 0x003 32 acr0 CREG 0x004 32 acr1 CREG 0x005 32 acr2 CREG 0x006 32 acr3 CREG 0x007 32 mmubar CREG 0x008 32 ; othera7 CREG 0x800 32 macsr CREG 0x804 32 mask CREG 0x805 32 acc0 CREG 0x806 32 accext01 CREG 0x807 32 accext23 CREG 0x808 32 acc1 CREG 0x809 32 acc2 CREG 0x80A 32 acc3 CREG 0x80B 32 ; fpu0 CREG 0x810 32 fpl0 CREG 0x811 32 fpu1 CREG 0x812 32 fpl1 CREG 0x813 32 fpu2 CREG 0x814 32 fpl2 CREG 0x815 32 fpu3 CREG 0x816 32 fpl3 CREG 0x817 32 fpu4 CREG 0x818 32 fpl4 CREG 0x819 32 fpu5 CREG 0x81a 32 fpl5 CREG 0x81b 32 fpu6 CREG 0x81c 32 fpl6 CREG 0x81d 32 fpu7 CREG 0x81e 32 fpl7 CREG 0x81f 32 fpiar CREG 0x821 32 fpsr CREG 0x822 32 fpcr CREG 0x824 32 ; rombar0 CREG 0xc00 32 rombar1 CREG 0xc01 32 rambar0 CREG 0xc04 32 rambar1 CREG 0xc05 32 ; ; ; DMM2 must be set to the MMU memory space ; mmucr DMM2 0x000 32 mmuor DMM2 0x004 32 mmusr DMM2 0x008 32 mmuar DMM2 0x010 32 mmutr DMM2 0x014 32 mmudr DMM2 0x018 32 ; ; DMM1 must be set to the internal memory base address ; ; System Integration Unit (SIU) sdramds1 DMM1 0x004 32 sbcr DMM1 0x010 32 cs0cfg01 DMM1 0x020 32 cs1cfg11 DMM1 0x024 32 cs2cfg21 DMM1 0x028 32 cs3cfg31 DMM1 0x02C 32 secsacr DMM1 0x038 32 rsr DMM1 0x044 32 jtagid DMM1 0x050 32 ; ; General PurposeTimers (GPT) gms0 DMM1 0x800 32 gcir0 DMM1 0x804 32 gpwm0 DMM1 0x808 32 gsr0 DMM1 0x80C 32 gms1 DMM1 0x810 32 gcir1 DMM1 0x814 32 gpwm1 DMM1 0x818 32 gsr1 DMM1 0x81C 32 gms2 DMM1 0x820 32 gcir2 DMM1 0x824 32 gpwm2 DMM1 0x828 32 gsr2 DMM1 0x82C 32 gms3 DMM1 0x830 32 gcir3 DMM1 0x834 32 gpwm3 DMM1 0x838 32 gsr3 DMM1 0x83C 32 ; ; Slice Timers (SLT) stcnt0 DMM1 0x900 32 scr0 DMM1 0x904 32 scnt0 DMM1 0x908 32 ssr0 DMM1 0x90C 32 stcnt1 DMM1 0x910 32 scr1 DMM1 0x914 32 scnt1 DMM1 0x918 32 ssr1 DMM1 0x91C 32 ; ; Interrupt Controller iprh DMM1 0x700 32 iprl DMM1 0x704 32 imrh DMM1 0x708 32 imrl DMM1 0x70C 32 intfrch DMM1 0x710 32 intfrcl DMM1 0x714 32 ilrr DMM1 0x718 8 iacklpr DMM1 0X719 8 ; icr01 DMM1 0x741 8 icr02 DMM1 0x742 8 icr03 DMM1 0x743 8 icr04 DMM1 0x744 8 icr05 DMM1 0x745 8 icr06 DMM1 0x746 8 icr07 DMM1 0x747 8 icr08 DMM1 0x748 8 icr09 DMM1 0x749 8 icr10 DMM1 0x74A 8 icr11 DMM1 0x74B 8 icr12 DMM1 0x74C 8 icr13 DMM1 0x74D 8 icr14 DMM1 0x74E 8 icr15 DMM1 0x74F 8 icr17 DMM1 0x751 8 icr18 DMM1 0x752 8 icr19 DMM1 0x753 8 icr20 DMM1 0x754 8 icr21 DMM1 0x755 8 icr22 DMM1 0x756 8 icr23 DMM1 0x757 8 icr24 DMM1 0x758 8 icr25 DMM1 0x759 8 icr26 DMM1 0x75A 8 icr27 DMM1 0x75B 8 icr28 DMM1 0x75C 8 icr29 DMM1 0x75D 8 icr30 DMM1 0x75E 8 icr31 DMM1 0x75F 8 icr32 DMM1 0x760 8 icr33 DMM1 0x761 8 icr34 DMM1 0x762 8 icr35 DMM1 0x763 8 icr36 DMM1 0x764 8 icr37 DMM1 0x765 8 icr38 DMM1 0x766 8 icr39 DMM1 0x767 8 icr40 DMM1 0x768 8 icr41 DMM1 0x769 8 icr42 DMM1 0x76A 8 icr43 DMM1 0x76B 8 icr44 DMM1 0x76C 8 icr45 DMM1 0x76D 8 icr46 DMM1 0x76E 8 icr47 DMM1 0x76F 8 icr48 DMM1 0x770 8 icr49 DMM1 0x771 8 icr50 DMM1 0x772 8 icr51 DMM1 0x773 8 icr52 DMM1 0x774 8 icr53 DMM1 0x775 8 icr54 DMM1 0x776 8 icr55 DMM1 0x777 8 icr56 DMM1 0x778 8 icr57 DMM1 0x779 8 icr58 DMM1 0x77A 8 icr59 DMM1 0x77B 8 icr60 DMM1 0x77C 8 icr61 DMM1 0x77D 8 icr62 DMM1 0x77E 8 icr63 DMM1 0x77F 8 ; ;swackr DMM1 0x7E0 8 ;l1iackr DMM1 0x7E4 8 ;l2iackr DMM1 0x7E8 8 ;l3iackr DMM1 0x7EC 8 ;l4iackr DMM1 0x7F0 8 ;l5iackr DMM1 0x7F4 8 ;l6iackr DMM1 0x7F8 8 ;l7iackr DMM1 0x7FC 8 ; ; Edge Port Module (EPORT) eppar DMM1 0xF00 16 epddr DMM1 0xF04 8 epier DMM1 0xF05 8 epdr DMM1 0xF08 8 eppdr DMM1 0xF09 8 epfr DMM1 0xF0C 8 ; ; GPIO podr_fbctl DMM1 0xA00 8 podr_fbcs DMM1 0xA01 8 podr_dma DMM1 0xA02 8 podr_fec0h DMM1 0xA04 8 podr_fec0l DMM1 0xA05 8 podr_fec1h DMM1 0xA06 8 podr_fec1l DMM1 0xA07 8 podr_feci2c DMM1 0xA08 8 podr_pcibg DMM1 0xA09 8 podr_pcibr DMM1 0xA0A 8 podr_psc3psc2 DMM1 0xA0C 8 podr_psc1psc0 DMM1 0xA0D 8 podr_dspi DMM1 0xA0E 8 ; pddr_fbctl DMM1 0xA10 8 pddr_fbcs DMM1 0xA11 8 pddr_dma DMM1 0xA12 8 pddr_fec0h DMM1 0xA14 8 pddr_fec0l DMM1 0xA15 8 pddr_fec1h DMM1 0xA16 8 pddr_fec1l DMM1 0xA17 8 pddr_feci2c DMM1 0xA18 8 pddr_pcibg DMM1 0xA19 8 pddr_pcibr DMM1 0xA1A 8 pddr_psc3psc2 DMM1 0xA1C 8 pddr_psc1psc0 DMM1 0xA1D 8 pddr_dspi DMM1 0xA1E 8 ; ppdsdr_fbctl DMM1 0xA20 8 ppdsdr_fbcs DMM1 0xA21 8 ppdsdr_dma DMM1 0xA22 8 ppdsdr_fec0h DMM1 0xA24 8 ppdsdr_fec0l DMM1 0xA25 8 ppdsdr_fec1h DMM1 0xA26 8 ppdsdr_fec1l DMM1 0xA27 8 ppdsdr_feci2c DMM1 0xA28 8 ppdsdr_pcibg DMM1 0xA29 8 ppdsdr_pcibr DMM1 0xA2A 8 ppdsdr_psc3psc2 DMM1 0xA2C 8 ppdsdr_psc1psc0 DMM1 0xA2D 8 ppdsdr_dspi DMM1 0xA2E 8 ; pclrr_fbctl DMM1 0xA30 8 pclrr_fbcs DMM1 0xA31 8 pclrr_dma DMM1 0xA32 8 pclrr_fec0h DMM1 0xA34 8 pclrr_fec0l DMM1 0xA35 8 pclrr_fec1h DMM1 0xA36 8 pclrr_fec1l DMM1 0xA37 8 pclrr_feci2c DMM1 0xA38 8 pclrr_pcibg DMM1 0xA39 8 pclrr_pcibr DMM1 0xA3A 8 pclrr_psc3psc2 DMM1 0xA3C 8 pclrr_psc1psc0 DMM1 0xA3D 8 pclrr_dspi DMM1 0xA3E 8 ; par_fbctl DMM1 0xA40 16 par_fbcs DMM1 0xA42 8 par_dma DMM1 0xA43 8 par_feci2cirq DMM1 0xA44 16 par_pcibg DMM1 0xA48 16 par_pcibr DMM1 0xA4A 8 par_psc3 DMM1 0xA4C 8 par_psc2 DMM1 0xA4D 8 par_psc1 DMM1 0xA4E 8 par_psc0 DMM1 0xA4F 8 par_dspi DMM1 0xA50 16 par_timer DMM1 0xA52 8 ; ; 32-Kbyte System SRAM sscr DMM1 0x1FFC0 16 tccr DMM1 0x1FFC4 32 tccrdr DMM1 0x1FFC8 32 tccrdw DMM1 0x1FFCC 32 tccrsec DMM1 0x1FFD0 32 ; ; FlexBus csar0 DMM1 0x500 16 csmr0 DMM1 0x504 32 cscr0 DMM1 0x508 32 csar1 DMM1 0x50C 16 csmr1 DMM1 0x510 32 cscr1 DMM1 0x514 32 csar2 DMM1 0x518 16 csmr2 DMM1 0x51C 32 cscr2 DMM1 0x520 32 csar3 DMM1 0x524 16 csmr3 DMM1 0x528 32 cscr3 DMM1 0x52C 32 csar4 DMM1 0x530 16 csmr4 DMM1 0x534 32 cscr4 DMM1 0x538 32 csar5 DMM1 0x53C 16 csmr5 DMM1 0x540 32 cscr5 DMM1 0x544 32 ; ; SDRAM Controller (SDRAMC) sdramds DMM1 0x004 32 cs0cfg DMM1 0x020 32 cs1cfg DMM1 0x024 32 cs2cfg DMM1 0x028 32 cs3cfg DMM1 0x02C 32 sdmr DMM1 0x100 32 sdcr DMM1 0x104 32 sdcfg1 DMM1 0x108 32 sdcfg2 DMM1 0x10C 32 ; ; Add more if you like ;)