;Register definition for IOP480 ;================================ ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IDCRx indirect accessed DCR's ; x = 1..4 ; the addr and data DCR is defined in the configuration file ; e.g. IDCR1 0x010 0x011 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; ; Special Purpose Registers ; cdbcr SPR 983 ctr SPR 9 dac SPR 1014 dbcr SPR 1010 dbsr SPR 1008 dccr SPR 1018 dcwr SPR 954 dear SPR 981 esr SPR 980 evpr SPR 982 iac SPR 1012 iccr SPR 1019 icdbdr SPR 979 lr SPR 8 pid SPR 945 pit SPR 987 pvr SPR 287 sgr SPR 953 skr SPR 956 sler SPR 955 sprg0 SPR 272 sprg1 SPR 273 sprg2 SPR 274 sprg3 SPR 275 srr0 SPR 26 srr1 SPR 27 srr2 SPR 990 srr3 SPR 991 tbhi SPR 988 tblo SPR 989 tcr SPR 986 tsr SPR 984 xer SPR 1 zpr SPR 944 ; ; ; ; Memory-Mapped Registers ; ; DMM1 must be set to the local PLX register base address ; ; Messaging Queue Registers ; mqcr DMM1 0x000 qbar DMM1 0x004 ifhpr DMM1 0x008 iftpr DMM1 0x00c iphpr DMM1 0x010 iptpr DMM1 0x014 ofhpr DMM1 0x018 oftpr DMM1 0x01c ophpr DMM1 0x020 optpr DMM1 0x024 qsr DMM1 0x028 ; opqis DMM1 0x030 opqim DMM1 0x034 iqpr DMM1 0x040 oqpr DMM1 0x044 hostoutidx DMM1 0x050 iopoutidx DMM1 0x054 ; ; Local Configuration Registers ; devint DMM1 0x080 locctl DMM1 0x084 loctmo DMM1 0x088 loctmr DMM1 0x08c larbr DMM1 0x090 bigend DMM1 0x094 pcictl DMM1 0x098 las0rr DMM1 0x0a0 las0ba DMM1 0x0a4 las1rr DMM1 0x0a8 las1ba DMM1 0x0ac las2rr DMM1 0x0b0 las2ba DMM1 0x0b4 eromrr DMM1 0x0c0 eromba DMM1 0x0c4 dmrr DMM1 0x0c8 dmlbam DMM1 0x0cc dmpbam DMM1 0x0d0 dmdac DMM1 0x0d4 dmlbai DMM1 0x0d8 dmcfga DMM1 0x0dc cfgba DMM1 0x0e0 uartba DMM1 0x0e4 plxid DMM1 0x0e8 plxrev DMM1 0x0ec ; ; Memory Controller Registers ; lcs0brd DMM1 0x100 lcs0wt DMM1 0x104 lcs0rt DMM1 0x108 lcs0base DMM1 0x10c lcs0range DMM1 0x110 lcs1brd DMM1 0x114 lcs1wt DMM1 0x118 lcs1rt DMM1 0x11c lcs1base DMM1 0x120 lcs1range DMM1 0x124 lcs2brd DMM1 0x128 lcs2wt DMM1 0x12c lcs2rt DMM1 0x130 lcs2base DMM1 0x134 lcs2range DMM1 0x138 lcs3brd DMM1 0x13c lcs3wt DMM1 0x140 lcs3rt DMM1 0x144 lcs3base DMM1 0x148 lcs3range DMM1 0x14c drambrd DMM1 0x150 dramctl DMM1 0x154 draminit DMM1 0x158 dramtim DMM1 0x15c drambase DMM1 0x160 dramrange DMM1 0x164 dfltbrd DMM1 0x168 ; ; Runtime Registers ; mbox0 DMM1 0x180 mbox1 DMM1 0x184 mbox2 DMM1 0x188 mbox3 DMM1 0x18c mbox4 DMM1 0x190 mbox5 DMM1 0x194 mbox6 DMM1 0x198 mbox7 DMM1 0x19c p2ldbell DMM1 0x1a0 l2pdbell DMM1 0x1a4 pintstat DMM1 0x1b0 pintenb DMM1 0x1b4 lintstat DMM1 0x1b8 lintenb DMM1 0x1bc pabtadr DMM1 0x1c0 ; ; DMA Registers ; c0mode DMM1 0x200 c0csr DMM1 0x204 c0count DMM1 0x208 c0pciladr DMM1 0x20c c0locadr DMM1 0x210 c0descptr DMM1 0x214 c0pcihadr DMM1 0x218 c0thres DMM1 0x21c c1mode DMM1 0x220 c1csr DMM1 0x224 c1count DMM1 0x228 c1pciladr DMM1 0x22c c1locadr DMM1 0x230 c1descptr DMM1 0x234 c1pcihadr DMM1 0x238 c1thres DMM1 0x23c c2mode DMM1 0x240 c2csr DMM1 0x244 c2count DMM1 0x248 c2srcadr DMM1 0x24c c2destadr DMM1 0x250 ; ; PCI Configuration Registers ; pciid DMM1 0x300 pcicr DMM1 0x304 pcirev DMM1 0x308 pciclsr DMM1 0x30c pcibar0 DMM1 0x310 pcibar1 DMM1 0x314 pcibar2 DMM1 0x318 pcisubid DMM1 0x32c pcierbar DMM1 0x330 pcicapptr DMM1 0x334 pciilr DMM1 0x33c pmcap DMM1 0x340 pmcsr DMM1 0x344 pmscale DMM1 0x348 pwrcon DMM1 0x34c pwrdis DMM1 0x350 hs0 DMM1 0x354 vpdcap DMM1 0x358 vpddata DMM1 0x35c ;