;Register definition for PPC405GP ;================================ ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IDCRx indirect accessed DCR's ; x = 1..4 ; the addr and data DCR is defined in the configuration file ; e.g. IDCR1 0x010 0x011 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; ; Special Purpose Registers ; ccr0 SPR 947 ctr SPR 9 dac1 SPR 1014 dac2 SPR 1015 dbcr0 SPR 1010 dbcr1 SPR 957 dccr SPR 1018 dcwr SPR 954 dvc1 SPR 950 dvc2 SPR 951 dear SPR 981 esr SPR 980 evpr SPR 982 iac1 SPR 1012 iac2 SPR 1013 iac3 SPR 948 iac4 SPR 949 iccr SPR 1019 icdbdr SPR 979 lr SPR 8 pit SPR 987 pvr SPR 287 sgr SPR 953 sler SPR 955 sprg0 SPR 272 sprg1 SPR 273 sprg2 SPR 274 sprg3 SPR 275 sprg4 SPR 276 sprg5 SPR 277 sprg6 SPR 278 sprg7 SPR 279 srr0 SPR 26 srr1 SPR 27 srr2 SPR 990 srr3 SPR 991 su0r SPR 956 tblr SPR 268 ;TBL read tblw SPR 284 ;TBL write tbur SPR 269 ;TBU read tbuw SPR 285 ;TBU write tcr SPR 986 tsr SPR 984 xer SPR 1 ; ; Directly Accessed DCR's ; memcfgadr DCR 0x010 memcfgdata DCR 0x011 ebccfgadr DCR 0x012 ebccfgdata DCR 0x013 kiar DCR 0x014 kidr DCR 0x015 ; pesr DCR 0x084 pear DCR 0x086 pacr DCR 0x087 gesr0 DCR 0x0A0 gear DCR 0x0A2 gesr1 DCR 0x0A4 ; pllmr DCR 0x0B0 chcr0 DCR 0x0B1 chcr1 DCR 0x0B2 chpsr DCR 0x0B4 cpmsr DCR 0x0B8 cpmer DCR 0x0B9 cpmfr DCR 0x0BA ; uicsr DCR 0x0C0 uicer DCR 0x0C2 uiccr DCR 0x0C3 uicpr DCR 0x0C4 uictr DCR 0x0C5 uicmsr DCR 0x0C6 uicvr DCR 0x0C7 uicvcr DCR 0x0C8 ; dmacr0 DCR 0x100 dmact0 DCR 0x101 dmada0 DCR 0x102 dmasa0 DCR 0x103 dmasb0 DCR 0x104 dmacr1 DCR 0x108 dmact1 DCR 0x109 dmada1 DCR 0x10A dmasa1 DCR 0x10B dmasb1 DCR 0x10C dmacr2 DCR 0x110 dmact2 DCR 0x111 dmada2 DCR 0x112 dmasa2 DCR 0x113 dmasb2 DCR 0x114 dmacr3 DCR 0x118 dmact3 DCR 0x119 dmada3 DCR 0x11A dmasa3 DCR 0x11B dmasb3 DCR 0x11C dmasr DCR 0x120 dmasgc DCR 0x123 dmaadr DCR 0x124 ; malcr DCR 0x180 malesr DCR 0x181 malier DCR 0x182 maltxeobisr DCR 0x186 maltxdeir DCR 0x187 malrxeobisr DCR 0x192 malrxdeir DCR 0x193 maltxctp0r DCR 0x1A0 maltxctp1r DCR 0x1A1 malrxctp0r DCR 0x1C0 malrcbs0 DCR 0x1E0 ; ; Indirectly Accessed DCR's ; ; IDCR1 must be set to MEMCFGADR and MEMCFGDATA ; IDCR2 must be set to EBCCFGADR and EBCCFGDATA ; IDCR3 must be set to KIAR and KIDR ; besra IDCR1 0x000 besrb IDCR1 0x008 bear IDCR1 0x010 mcopt1 IDCR1 0x020 rtr IDCR1 0x030 pmit IDCR1 0x034 mb0cf IDCR1 0x040 mb1cf IDCR1 0x044 mb2cf IDCR1 0x048 mb3cf IDCR1 0x04C mb4cf IDCR1 0x050 mb5cf IDCR1 0x054 mb6cf IDCR1 0x058 mb7cf IDCR1 0x05C sdtr1 IDCR1 0x080 ecccf IDCR1 0x094 eccerr IDCR1 0x098 ; pb0cr IDCR2 0x000 pb1cr IDCR2 0x001 pb2cr IDCR2 0x002 pb3cr IDCR2 0x003 pb4cr IDCR2 0x004 pb5cr IDCR2 0x005 pb6cr IDCR2 0x006 pb7cr IDCR2 0x007 pb0ap IDCR2 0x010 pb1ap IDCR2 0x011 pb2ap IDCR2 0x012 pb3ap IDCR2 0x013 pb4ap IDCR2 0x014 pb5ap IDCR2 0x015 pb6ap IDCR2 0x016 pb7ap IDCR2 0x017 pbear IDCR2 0x020 pbesr0 IDCR2 0x021 pbesr1 IDCR2 0x022 epcr IDCR2 0x023 ; kitor0 IDCR3 0x000 kitor1 IDCR3 0x001 kitor2 IDCR3 0x002 kitor3 IDCR3 0x003 kaddr0 IDCR3 0x004 kaddr1 IDCR3 0x005 kconf IDCR3 0x040 kid IDCR3 0x041 kver IDCR3 0x042 kpear IDCR3 0x050 kbear IDCR3 0x051 kesr0 IDCR3 0x052 ; ; Memory-Mapped Registers ; pcicfgadr MM 0xEEC00000 32 pcicfgdata MM 0xEEC00004 32 ; pmm0la MM 0xEF400000 32 pmm0ma MM 0xEF400004 32 pmm0pcila MM 0xEF400008 32 pmm0pciha MM 0xEF40000C 32 pmm1la MM 0xEF400010 32 pmm1ma MM 0xEF400014 32 pmm1pcila MM 0xEF400018 32 pmm1pciha MM 0xEF40001C 32 pmm2la MM 0xEF400020 32 pmm2ma MM 0xEF400024 32 pmm2pcila MM 0xEF400028 32 pmm2pciha MM 0xEF40002C 32 ptm1ms MM 0xEF400030 32 ptm1la MM 0xEF400034 32 ptm2ms MM 0xEF400038 32 ptm2la MM 0xEF40003C 32 ; uart0rbr MM 0xEF600300 8 uart0thr MM 0xEF600300 8 uart0dll MM 0xEF600300 8 uart0ier MM 0xEF600301 8 uart0dlm MM 0xEF600301 8 uart0iir MM 0xEF600302 8 uart0fcr MM 0xEF600302 8 uart0lcr MM 0xEF600303 8 uart0mcr MM 0xEF600304 8 usrt0lsr MM 0xEF600305 8 uart0msr MM 0xEF600306 8 uart0scr MM 0xEF600307 8 uart1rbr MM 0xEF600400 8 uart1thr MM 0xEF600400 8 uart1dll MM 0xEF600400 8 uart1ier MM 0xEF600401 8 uart1dlm MM 0xEF600401 8 uart1iir MM 0xEF600402 8 uart1fcr MM 0xEF600402 8 uart1lcr MM 0xEF600403 8 uart1mcr MM 0xEF600404 8 usrt1lsr MM 0xEF600405 8 uart1msr MM 0xEF600406 8 uart1scr MM 0xEF600407 8 ; iic0mdbuf MM 0xEF600500 8 iic0sdbuf MM 0xEF600502 8 iic0lmadr MM 0xEF600504 8 iic0hmadr MM 0xEF600505 8 iic0cntl MM 0xEF600506 8 iic0mdcntl MM 0xEF600507 8 iic0sts MM 0xEF600508 8 iic0extsts MM 0xEF600509 8 iic0lsadr MM 0xEF60050A 8 iic0hsadr MM 0xEF60050B 8 iic0clkdiv MM 0xEF60050C 8 iic0intrmsk MM 0xEF60050D 8 iic0xfrcnt MM 0xEF60050E 8 iic0xtcntlss MM 0xEF60050F 8 iic0directcntl MM 0xEF600510 8 ; oapr MM 0xEF600600 8 oacr MM 0xEF600601 8 ; gpo MM 0xEF600700 32 gptc MM 0xEF600704 32 gpod MM 0xEF600718 32 gpi MM 0xEF60071C 32 ; em0mr0 MM 0xEF600800 32 em0mr1 MM 0xEF600804 32 em0tmr0 MM 0xEF600808 32 em0tmr1 MM 0xEF60080C 32 em0rmr MM 0xEF600810 32 em0isr MM 0xEF600814 32 em0iser MM 0xEF600818 32 em0iah MM 0xEF60081C 32 em0ial MM 0xEF600820 32 em0vtpid MM 0xEF600824 32 em0vtci MM 0xEF600828 32 em0ptr MM 0xEF60082C 32 em0iaht1 MM 0xEF600830 32 em0iaht2 MM 0xEF600834 32 em0iaht3 MM 0xEF600838 32 em0iaht4 MM 0xEF60083C 32 em0gaht1 MM 0xEF600840 32 em0gaht2 MM 0xEF600844 32 em0gaht3 MM 0xEF600848 32 em0gaht4 MM 0xEF60084C 32 em0lsah MM 0xEF600850 32 em0lsal MM 0xEF600854 32 em0ipgvr MM 0xEF600858 32 em0scr MM 0xEF60085C 32 em0trtr MM 0xEF600860 32 em0rwmr MM 0xEF600864 32 ;