;Register definition for PPC405EP ;================================ ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IDCRx indirect accessed DCR's ; x = 1..4 ; the addr and data DCR is defined in the configuration file ; e.g. IDCR1 0x010 0x011 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; R0 GPR 0 R1 GPR 1 R2 GPR 2 R3 GPR 3 R4 GPR 4 R5 GPR 5 R6 GPR 6 R7 GPR 7 R8 GPR 8 R9 GPR 9 R10 GPR 10 R11 GPR 11 R12 GPR 12 R13 GPR 13 R14 GPR 14 R15 GPR 15 R16 GPR 16 R17 GPR 17 R18 GPR 18 R19 GPR 19 R20 GPR 20 R21 GPR 21 R22 GPR 22 R23 GPR 23 R24 GPR 24 R25 GPR 25 R26 GPR 26 R27 GPR 27 R28 GPR 28 R29 GPR 29 R30 GPR 30 R31 GPR 31 ; ; Special Purpose Registers ; Mnemonic REG TYP Decimal Register Name CCR0 SRP 947 ; Core Configuration Register 0 CTR SRP 9 ; Count Register DAC1 SRP 1014 ; Data Address Compare 1 DAC2 SRP 1015 ; Data Address Compare 2 DBCR0 SRP 1010 ; Debug Control Register 0 DBCR1 SRP 957 ; Debug Control Register 1 DBSR SRP 1008 ; Debug Status Register DCCR SRP 1018 ; Data Cache Cachability Register DCWR SRP 954 ; Data Cache Write-through Register DVC1 SRP 950 ; Data Value Compare 1 DVC2 SRP 951 ; Data Value Compare 2 DEAR SRP 981 ; Data Error Address Register ESR SRP 980 ; Exception Syndrome Register EVPR SRP 982 ; Exception Vector Prefix Register IAC1 SRP 1012 ; Instruction Address Compare 1 IAC2 SRP 1013 ; Instruction Address Compare 2 IAC3 SRP 948 ; Instruction Address Compare 3 IAC4 SRP 949 ; Instruction Address Compare 4 ICCR SRP 1019 ; Instruction Cache Cachability Register ICDBDR SRP 979 ; Instruction Cache Debug Data Register LR SRP 8 ; Link Register PID SRP 945 ; Process ID PIT SRP 987 ; Programmable Interval Timer PVR SRP 287 ; Processor Version Register SGR SRP 953 ; Storage Guarded Register SLER SRP 955 ; Storage Little Endian Register SPRG0 SRP 272 ; SPR General 0 SPRG1 SRP 273 ; SPR General 1 SPRG2 SRP 274 ; SPR General 2 SPRG3 SRP 275 ; SPR General 3 SPRG4 SRP 260 ; SPR General 4 SPRG4 SRP 276 ; SPR General 4 SPRG5 SRP 261 ; SPR General 5 SPRG5 SRP 277 ; SPR General 5 SPRG6 SRP 262 ; SPR General 6 SPRG6 SRP 278 ; SPR General 6 SPRG7 SRP 263 ; SPR General 7 SPRG7 SRP 279 ; SPR General 7 SRR0 SRP 26 ; Save/Restore Register 0 SRR1 SRP 27 ; Save/Restore Register 1 SRR2 SRP 990 ; Save/Restore Register 2 SRR3 SRP 991 ; Save/Restore Register 3 SU0R SRP 956 ; Storage User-defined 0 Register TBL SRP 284 ; Time Base Lower TBU SRP 285 ; Time Base Upper TCR SRP 986 ; Timer Control Register TSR SRP 984 ; Timer Status Register USPRG0 SRP 256 ; User SPR General 0 XER SRP 1 ; Fixed Point Exception Register ZPR SRP 944 ; Zone Protection Register ; ; DCRs Used for Direct Access ; ;DCRs Used for inirect Access SDRAM0_CFGADDR DCR 0x010 ; Memory Controller Address Register SDRAM0_CFGDATA DCR 0x011 ; Memory Controller Data Register EBC0_CFGADDR DCR 0x012 ; Peripheral Controller Address Register EBC0_CFGDATA DCR 0x013 ; Peripheral Controller Data Register ; On-Chip Buses PLB0_BESR DCR 0x084 ; PLB Bus Error Status Register PLB0_BEAR DCR 0x086 ; PLB Bus Error Address Register PLB0_ACR DCR 0x087 ; PLB Arbiter Control Register POB0_BESR0 DCR 0x0A0 ; PLB to OPB Bus Error Status Register 0 POB0_BEAR DCR 0x0A2 ; PLB to OPB Bus Error Address Register POB0_BESR1 DCR 0x0A4 ; PLB to OPB Bus Error Status Register 1 ; Clocking and Chip Control CPC0_PLLMR0 DCR 0x0F0 ; PLL Mode Register 0 CPC0_BOOT DCR 0x0F1 ; Clock Status Register CPC0_EPCTL DCR 0x0F3 ; EMAC PHY Receive Clock Source Register CPC0_PLLMR1 DCR 0x0F4 ; PLL Mode Register 1 CPC0_UCR DCR 0x0F5 ; UART Control Register CPC0_SRR DCR 0x0F6 ; Soft Reset Register CPC0_JTAGID DCR 0x0F7 ; JTAG ID Register CPC0_PCI DCR 0x0F9 ; PCI Control Register ; Clock and Power Management CPC0_ER DCR 0x0B8 ; CPM Enable Register CPC0_FR DCR 0x0B9 ; CPM Force Register CPC0_SR DCR 0x0BA ; CPM Status Register ; Universal Interrupt Controllers UIC0_SR DCR 0x0C0 ; UIC0 Status Register UIC0_ER DCR 0x0C2 ; UIC0 Enable Register UIC0_CR DCR 0x0C3 ; UIC0 Critical Register UIC0_PR DCR 0x0C4 ; UIC0 Polarity Register UIC0_TR DCR 0x0C5 ; UIC0 Triggering Register UIC0_MSR DCR 0x0C6 ; UIC0 Masked Status Register UIC0_VR DCR 0x0C7 ; UIC0 Vector Register UIC0_VCR DCR 0x0C8 ; UIC0 Vector Configuration Register ; Direct Memory Access DMA0_CR0 DCR 0x100 ; DMA Channel Control Register 0 DMA0_CT0 DCR 0x101 ; DMA Count Register 0 DMA0_DA0 DCR 0x102 ; DMA Destination Address Register 0 DMA0_SA0 DCR 0x103 ; DMA Source Address Register 0 DMA0_SG0 DCR 0x104 ; DMA Scatter/Gather Descriptor Address Register 0 DMA0_CR1 DCR 0x108 ; DMA Channel Control Register 1 DMA0_CT1 DCR 0x109 ; DMA Count Register 1 DMA0_DA1 DCR 0x10A ; DMA Destination Address Register 1 DMA0_SA1 DCR 0x10B ; DMA Source Address Register 1 DMA0_SG1 DCR 0x10C ; DMA Scatter/Gather Descriptor Address Register 1 DMA0_CR2 DCR 0x110 ; DMA Channel Control Register 2 DMA0_CT2 DCR 0x111 ; DMA Count Register 2 DMA0_DA2 DCR 0x112 ; DMA Destination Address Register 2 DMA0_SA2 DCR 0x113 ; DMA Source Address Register 2 DMA0_SG2 DCR 0x114 ; DMA Scatter/Gather Descriptor Address Register 2 DMA0_CR3 DCR 0x118 ; DMA Channel Control Register 3 DMA0_CT3 DCR 0x119 ; DMA Count Register 3 DMA0_DA3 DCR 0x11A ; DMA Destination Address Register 3 DMA0_SA3 DCR 0x11B ; DMA Source Address Register 3 DMA0_SG3 DCR 0x11C ; DMA Scatter/Gather Descriptor Address DMA0_SR DCR 0x120 ; DMA Status Register DMA0_SGC DCR 0x123 ; DMA Scatter/Gather Command Register DMA0_SLP DCR 0x125 ; DMA Sleep Mode Register ; On-Chip Memory OCM0_ISARC DCR 0x018 ; OCM Instruction-Side Address Range Compare Register OCM0_ISCNTL DCR 0x019 ; OCM Instruction-Side Control Register OCM0_DSARC DCR 0x01A ; OCM Data-Side Address Range Compare Register OCM0_DSCNTL DCR 0x01B ; OCM Data-Side Control Register ; Memory Access Layer MAL0_CFG DCR 0x180 ; MAL Configuration Register MAL0_ESR DCR 0x181 ; Error Status Register MAL0_IER DCR 0x182 ; Interrupt Enable Register MAL0_TXCASR DCR 0x184 ; Tx Channel Active Register (Set) MAL0_TXCARR DCR 0x185 ; Tx Channel Active Register (Reset) MAL0_TXEOBISR DCR 0x186 ; Tx End of Buffer Interrupt Status Register MAL0_TXDEIR DCR 0x187 ; Tx Descriptor Error Interrupt Register MAL0_RXCASR DCR 0x190 ; Rx Channel Active Register (Set) MAL0_RXCARR DCR 0x191 ; Rx Channel Active Register (Reset) MAL0_RXEOBISR DCR 0x192 ; Rx End of Buffer Interrupt Status Register MAL0_RXDEIR DCR 0x193 ; Rx Descriptor Error Interrupt Register MAL0_TXCTP0R DCR 0x1A0 ; Channel Tx 0 Channel Table Pointer Register MAL0_TXCTP1R DCR 0x1A1 ; Channel Tx 1 Channel Table Pointer Register MAL0_TXCTP2R DCR 0x1A2 ; Channel Tx 2 Channel Table Pointer Register MAL0_TXCTP3R DCR 0x1A3 ; Channel Tx 3Channel Table Pointer Register MAL0_RXCTP0R DCR 0x1C0 ; Channel Rx 0 Channel Table Pointer Register MAL0_RXCTP1R DCR 0x1C1 ; Channel Rx 1 Channel Table Pointer Register MAL0_RCBS0 DCR 0x1E0 ; Channel RX 0 Channel Buffer Size Register MAL0_RCBS1 DCR 0x1E1 ; Channel RX 1 Channel Buffer Size Register ; Event Counters EVC0_CNT0 DCR 0x200 ; Event Counter 0 EVC0_CNT1 DCR 0x201 ; Event Counter 1 EVC0_ECR DCR 0x202 ; Event Counter Control Register ; ; Indirectly Accessed DCR's ; ; IDCR1 must be set to SDRAM0_CFGADDR and SDRAM0_CFGDATA ; In the [REGS] section of the config file define an entry ; IDCR1 0x010 0x011 ;SDRAM0_CFGADDR and SDRAM0_CFGDATA ; SDRAM0_CFG IDCR1 0x20 ; Memory Controller Options 1 SDRAM0_STATUS IDCR1 0x24 ; SDRAM Controller Status SDRAM0_RTR IDCR1 0x30 ; Refresh Timer Register SDRAM0_PMIT IDCR1 0x34 ; Power Management Idle Timer SDRAM0_B0CR IDCR1 0x40 ; Memory Bank 0 Configuration Register SDRAM0_B1CR IDCR1 0x44 ; Memory Bank 1 Configuration Register SDRAM0_TR IDCR1 0x80 ; SDRAM Timing Register 1 ; ; IDCR2 must be set to EBC0_CFGADDR and EBC0_CFGDATA ; In the [REGS] section of the config file define an entry ; IDCR2 0x012 0x013 ;EBC0_CFGADDR and EBC0_CFGDATA ; EBC0_B0CR IDCR2 0x00 ; Peripheral Bank 0 Configuration Register EBC0_B1CR IDCR2 0x01 ; Peripheral Bank 1 Configuration Register EBC0_B2CR IDCR2 0x02 ; Peripheral Bank 2 Configuration Register EBC0_B3CR IDCR2 0x03 ; Peripheral Bank 3 Configuration Register EBC0_B4CR IDCR2 0x04 ; Peripheral Bank 4 Configuration Register EBC0_B0AP IDCR2 0x10 ; Peripheral Bank 0 Access Parameters EBC0_B1AP IDCR2 0x11 ; Peripheral Bank 1 Access Parameters EBC0_B2AP IDCR2 0x12 ; Peripheral Bank 2 Access Parameters EBC0_B3AP IDCR2 0x13 ; Peripheral Bank 3 Access Parameters EBC0_B4AP IDCR2 0x14 ; Peripheral Bank 4 Access Parameters EBC0_BEAR IDCR2 0x20 ; Peripheral Bus Error Address Register EBC0_BESR0 IDCR2 0x21 ; Peripheral Bus Error Status Register 0 EBC0_BESR1 IDCR2 0x22 ; Peripheral Bus Error Status Register 1 EBC0_CFG IDCR2 0x23 ; External Peripheral Control Register ; ; Memory-Mapped Registers ; pcicfgadr MM 0xEEC00000 32 pcicfgdata MM 0xEEC00004 32 ; pmm0la MM 0xEF400000 32 pmm0ma MM 0xEF400004 32 pmm0pcila MM 0xEF400008 32 pmm0pciha MM 0xEF40000C 32 pmm1la MM 0xEF400010 32 pmm1ma MM 0xEF400014 32 pmm1pcila MM 0xEF400018 32 pmm1pciha MM 0xEF40001C 32 pmm2la MM 0xEF400020 32 pmm2ma MM 0xEF400024 32 pmm2pcila MM 0xEF400028 32 pmm2pciha MM 0xEF40002C 32 ptm1ms MM 0xEF400030 32 ptm1la MM 0xEF400034 32 ptm2ms MM 0xEF400038 32 ptm2la MM 0xEF40003C 32 ; uart0rbr MM 0xEF600300 8 uart0thr MM 0xEF600300 8 uart0dll MM 0xEF600300 8 uart0ier MM 0xEF600301 8 uart0dlm MM 0xEF600301 8 uart0iir MM 0xEF600302 8 uart0fcr MM 0xEF600302 8 uart0lcr MM 0xEF600303 8 uart0mcr MM 0xEF600304 8 usrt0lsr MM 0xEF600305 8 uart0msr MM 0xEF600306 8 uart0scr MM 0xEF600307 8 uart1rbr MM 0xEF600400 8 uart1thr MM 0xEF600400 8 uart1dll MM 0xEF600400 8 uart1ier MM 0xEF600401 8 uart1dlm MM 0xEF600401 8 uart1iir MM 0xEF600402 8 uart1fcr MM 0xEF600402 8 uart1lcr MM 0xEF600403 8 uart1mcr MM 0xEF600404 8 usrt1lsr MM 0xEF600405 8 uart1msr MM 0xEF600406 8 uart1scr MM 0xEF600407 8 ; iic0mdbuf MM 0xEF600500 8 iic0sdbuf MM 0xEF600502 8 iic0lmadr MM 0xEF600504 8 iic0hmadr MM 0xEF600505 8 iic0cntl MM 0xEF600506 8 iic0mdcntl MM 0xEF600507 8 iic0sts MM 0xEF600508 8 iic0extsts MM 0xEF600509 8 iic0lsadr MM 0xEF60050A 8 iic0hsadr MM 0xEF60050B 8 iic0clkdiv MM 0xEF60050C 8 iic0intrmsk MM 0xEF60050D 8 iic0xfrcnt MM 0xEF60050E 8 iic0xtcntlss MM 0xEF60050F 8 iic0directcntl MM 0xEF600510 8 ; oapr MM 0xEF600600 8 oacr MM 0xEF600601 8 ; gpo MM 0xEF600700 32 gptc MM 0xEF600704 32 gpod MM 0xEF600718 32 gpi MM 0xEF60071C 32 ; em0mr0 MM 0xEF600800 32 em0mr1 MM 0xEF600804 32 em0tmr0 MM 0xEF600808 32 em0tmr1 MM 0xEF60080C 32 em0rmr MM 0xEF600810 32 em0isr MM 0xEF600814 32 em0iser MM 0xEF600818 32 em0iah MM 0xEF60081C 32 em0ial MM 0xEF600820 32 em0vtpid MM 0xEF600824 32 em0vtci MM 0xEF600828 32 em0ptr MM 0xEF60082C 32 em0iaht1 MM 0xEF600830 32 em0iaht2 MM 0xEF600834 32 em0iaht3 MM 0xEF600838 32 em0iaht4 MM 0xEF60083C 32 em0gaht1 MM 0xEF600840 32 em0gaht2 MM 0xEF600844 32 em0gaht3 MM 0xEF600848 32 em0gaht4 MM 0xEF60084C 32 em0lsah MM 0xEF600850 32 em0lsal MM 0xEF600854 32 em0ipgvr MM 0xEF600858 32 em0scr MM 0xEF60085C 32 em0trtr MM 0xEF600860 32 em0rwmr MM 0xEF600864 32 ;