;************************************************************** ; bdiGDB configuration file for RPXlite w 64Mb RAM, 16Mb Flash ;************************************************************** [INIT] ;============================================================== ; init core register ;----------------------------------------------------- WREG MSR 0x00000002 ;MSR : RI WSPR 27 0x00001002 ;SRR1 : ME,RI WSPR 149 0x2006000F ;DER : enable SYSIE for BDI flash progr. (bit13) WSPR 158 0x00000007 ;ICTRL: WSPR 638 0xFA200000 ;IMMR : ; init SIU register ;----------------------------------------------------- WM32 0xFA200000 0x00000800 ;SIUMCR WM32 0xFA200004 0xFFFFFF88 ;SYPCR WM32 0xFA200280 0x02020000 ;SCCR: WM32 0xFA200284 0x0070d000 ;PLPRCR no need to change (1:1 clock mode) WM32 0xFA2000E0 0X00000000 ;PGCRA Disable PCMCIA buffers WM32 0xFA2000E4 0X00000080 ;PGCRB Disable PCMCIA buffers ;WM16 0xFA200200 0x00C3 ;TBSCR: stop timebase and decrementer while freeze is asserted ;WM16 0xFA200220 0x00C1 ;RTCSC: stop real-time clock while freeze is asserted ;WM16 0xFA200240 0x0083 ;PISCR: stop periodic interrupt while freeze is asserted ;WM32 0xFA200320 0x55CCAA33 ;RTCSCK: unlock real-time clock status and control register ;WM32 0xFA200324 0x55CCAA33 ;RTCK: unlock real-Time clock register ;WM32 0xFA200328 0x55CCAA33 ;RTSECK: unlock real-time alarm seconds ;WM32 0xFA20032C 0x55CCAA33 ;RTCALK: unlock real-time alarm register ; init UPM ;----------------------------------------------------- SUPM 0xFA200168 0xFA20017c ; set address for MCR and MDR WUPM 0x00000000 0x0F03CC04 ; UPMA single read WUPM 0x00000001 0x00ACCC24 WUPM 0x00000002 0x1FF74C20 WUPM 0x00000003 0xFFFFCC25 WUPM 0x00000004 0xFFFFCC25 WUPM 0x00000005 0xFFFFCC25 WUPM 0x00000006 0xFFFFCC25 WUPM 0x00000007 0xFFFFCC25 WUPM 0x00000008 0x0F03CC04 ; burst read. (offset 8 in UPMA RAM) WUPM 0x00000009 0x00ACCC24 WUPM 0x0000000A 0x00FFCC20 WUPM 0x0000000B 0x00FFCC20 WUPM 0x0000000C 0x01FFCC20 WUPM 0x0000000D 0x1FF74C20 WUPM 0x0000000E 0xFFFFCC25 WUPM 0x0000000F 0xFFFFCC25 WUPM 0x00000010 0xFFFFCC25 WUPM 0x00000011 0xFFFFCC25 WUPM 0x00000012 0xFFFFCC25 WUPM 0x00000013 0xFFFFCC25 WUPM 0x00000014 0xFFFFCC25 WUPM 0x00000015 0xFFFFCC25 WUPM 0x00000016 0xFFFFCC25 WUPM 0x00000017 0xFFFFCC25 WUPM 0x00000018 0x0F03CC02 ; single write. (offset 18 in UPMA RAM) WUPM 0x00000019 0x00AC0C24 WUPM 0x0000001A 0x1FF74C25 WUPM 0x0000001B 0xFFFFCC25 WUPM 0x0000001C 0xFFFFCC25 WUPM 0x0000001D 0xFFFFCC25 WUPM 0x0000001E 0xFFFFCC25 WUPM 0x0000001F 0xFFFFCC25 WUPM 0x00000020 0x0F03CC00 ; burst write. (offset 20 in UPMA RAM) WUPM 0x00000021 0x00AC0C20 WUPM 0x00000022 0x00FFFC20 WUPM 0x00000023 0x00FFFC22 WUPM 0x00000024 0x01FFFC24 WUPM 0x00000025 0x1FF74C25 WUPM 0x00000026 0xFFFFCC25 WUPM 0x00000027 0xFFFFCC25 WUPM 0x00000028 0xFFFFCC25 WUPM 0x00000029 0xFFFFCC25 WUPM 0x0000002A 0xFFFFCC25 WUPM 0x0000002B 0xFFFFCC25 WUPM 0x0000002C 0xFFFFCC25 WUPM 0x0000002D 0xFFFFCC25 WUPM 0x0000002E 0xFFFFCC25 WUPM 0x0000002F 0xFFFFCC25 WUPM 0x00000030 0x0FF0CC24 ; refresh (offset 30 in UPMA RAM) WUPM 0x00000031 0xFFFFCC24 WUPM 0x00000032 0xFFFFCC25 WUPM 0x00000033 0xFFFFCC25 WUPM 0x00000034 0xFFFFCC25 WUPM 0x00000035 0xFFFFCC25 WUPM 0x00000036 0xEFFB8C34 ; SDRAM Load Command (offset 36) WUPM 0x00000037 0x0FF74C34 WUPM 0x00000038 0x0FFACCB4 WUPM 0x00000039 0x0FF5CC34 WUPM 0x0000003A 0x0FFFCC34 WUPM 0x0000003B 0x0FFFCCB4 WUPM 0x0000003C 0x0FEA8C34 ; exception. (offset 3c in UPMA RAM) WUPM 0x0000003D 0x1FB54C34 WUPM 0x0000003E 0xFFFFCC34 WUPM 0x0000003F 0xFFFFCC25 ; Init SDRAM: ;----------------------------------------------------- WM16 0xfa20017A 0x2000 ;mptpr WM32 0xfa200170 0x20904000 ;mamr WM32 0xfa200174 0x74001000 ;mbmr WM32 0xfa200164 0x00000088 ;mar WM32 0xfa200168 0x80002236 ;mcr WM32 0xfa200164 0x00000088 ;mar ; Init Memory Controller: ;----------------------------------------------------- ; OR0 and BR0 (FLASH) WM32 0xFA200104 0xFC000120 WM32 0xFA200100 0xFC004001 ; OR1 and BR1 (SDRAM) WM32 0xFA20010C 0xFC000E00 WM32 0xFA200108 0x00000081 ; OR2 and BR2 (invalid) WM32 0xFA200114 0x00000000 WM32 0xFA200110 0x00000000 ; OR3 and BR3 (Board Specific regs) WM32 0xFA20011C 0xFF7F8940 WM32 0xFA200118 0xFA400001 ; OR4 and BR4 (NVRAM) WM32 0xFA200124 0xFFFE0040 WM32 0xFA200120 0xFA000401 [TARGET] ;============================================================== CPUTYPE MPC800 CPUCLOCK 8000000 ;CPU clock rate after processing the init list BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoints ;STARTUP RESET [HOST] ;============================================================== IP 192.168.1.1 FILE PCB8xx202.ep FORMAT SREC LOAD MANUAL ;load code MANUAL or AUTO after reset ;START 0x100000 DUMP dump.txt [FLASH] ;============================================================== CHIPTYPE AM29BX8 ;Flash type (AM29DL323DB) CHIPSIZE 0x400000 ;The size of one flash chip in bytes BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32) ;WORKSPACE 0x01002000 ; RAM buffer for fast flash programming FILE u-boot.bin ;The file to program FORMAT BIN 0x00000000 ERASE 0xFF000000 SECTOR ; Erase the BootLoader ;ERASE 0xFF000000 0x00010000 4 ; Erase the BootLoader [REGS] DMM1 0xFA200000 FILE reg860.def