;Register definition for PPC440GX ;========================================== ;All PCI Registers were added the this file ;Need to add PMM2 0x1EEC0 and PMM3 0x1EF40 to Config file (reg440epx.cfg) ; ; ; name: user defined name of the register ; type: the type of the register ; GPR general purpose register ; SPR special purpose register ; MM memory mapped register ; DMMx direct memory mapped register with offset ; x = 1..4 ; the base is defined in the configuration file ; e.g. DMM1 0x02200000 ; IDCRx indirect accessed DCR's ; x = 1..4 ; the addr and data DCR is defined in the configuration file ; e.g. IDCR1 0x010 0x011 ; addr: the number, adddress or offset of the register ; size the size of the register (8,16 or 32) ; ;name type addr size ;------------------------------------------- ; sp GPR 1 ; ; Special Purpose Registers ; xer SPR 0x001 lr SPR 0x008 ctr SPR 0x009 dec SPR 0x016 srr0 SPR 0x01a srr1 SPR 0x01b pid SPR 0x030 decar SPR 0x036 csrr0 SPR 0x03a csrr1 SPR 0x03b dear SPR 0x03d esr SPR 0x03e ivpr SPR 0x03f usprg0 SPR 0x100 sprg4r SPR 0x104 sprg5r SPR 0x105 sprg6r SPR 0x106 sprg7r SPR 0x107 tblr SPR 0x10c tbur SPR 0x10d sprg0 SPR 0x110 sprg1 SPR 0x111 sprg2 SPR 0x112 sprg3 SPR 0x113 sprg4w SPR 0x114 sprg5w SPR 0x115 sprg6w SPR 0x116 sprg7w SPR 0x117 tblw SPR 0x11c tbuw SPR 0x11d pir SPR 0x11e pvr SPR 0x11f dbsr SPR 0x130 dbcr0 SPR 0x134 dbcr1 SPR 0x135 dbcr2 SPR 0x136 iac1 SPR 0x138 iac2 SPR 0x139 iac3 SPR 0x13a iac4 SPR 0x13b dac1 SPR 0x13c dac2 SPR 0x13d dvc1 SPR 0x13e dvc2 SPR 0x13f tsr SPR 0x150 tcr SPR 0x154 ivor0 SPR 0x190 ivor1 SPR 0x191 ivor2 SPR 0x192 ivor3 SPR 0x193 ivor4 SPR 0x194 ivor5 SPR 0x195 ivor6 SPR 0x196 ivor7 SPR 0x197 ivor8 SPR 0x198 ivor9 SPR 0x199 ivor10 SPR 0x19a ivor11 SPR 0x19b ivor12 SPR 0x19c ivor13 SPR 0x19d ivor14 SPR 0x19e ivor15 SPR 0x19f mcsrr0 SPR 0x23a mcsrr1 SPR 0x23b mcsr SPR 0x23c inv0 SPR 0x370 inv1 SPR 0x371 inv2 SPR 0x372 inv3 SPR 0x373 itv0 SPR 0x374 itv1 SPR 0x375 itv2 SPR 0x376 itv3 SPR 0x377 ccr1 SPR 0x378 dnv0 SPR 0x390 dnv1 SPR 0x391 dnv2 SPR 0x392 dnv3 SPR 0x393 dtv0 SPR 0x394 dtv1 SPR 0x395 dtv2 SPR 0x396 dtv3 SPR 0x397 dvlim SPR 0x398 ivlim SPR 0x399 rstcfg SPR 0x39b dcdbtrl SPR 0x39c dcdbtrh SPR 0x39d icdbtrl SPR 0x39e icdbtrh SPR 0x39f mmucr SPR 0x3b2 ccr0 SPR 0x3b3 icdbdr SPR 0x3d3 dbdr SPR 0x3f3 ; ; Directly Accessed DCR's ; cpr0_cfgaddr DCR 0x00C cpr0_cfgdata DCR 0x00D sdr0_cfgaddr DCR 0x00E sdr0_cfgdata DCR 0x00F sdram0_cfgaddr DCR 0x010 sdram0_cfgdata DCR 0x011 ebc0_cfgaddr DCR 0x012 ebc0_cfgdata DCR 0x013 ebm0_cfgaddr DCR 0x014 ebm0_cfgdata DCR 0x015 ppm0_cfgaddr DCR 0x016 ppm0_cfgdata DCR 0x017 ; ; Internal SRAM Controller ; sram0_sb0cr DCR 0x020 sram0_sb1cr DCR 0x021 sram0_sb2cr DCR 0x022 sram0_sb3cr DCR 0x023 sram0_bear DCR 0x024 sram0_besr0 DCR 0x025 sram0_besr1 DCR 0x026 sram0_pmeg DCR 0x027 sram0_dpc DCR 0x0a0 ; ; On-Chip Buses ; plb0_revid DCR 0x082 plb0_acr DCR 0x083 plb0_besr DCR 0x084 plb0_bearl DCR 0x086 plb0_bearh DCR 0x087 pob0_besr0 DCR 0x090 pob0_bearl DCR 0x092 pob0_bearh DCR 0x093 pob0_besr1 DCR 0x094 pob0_confg DCR 0x096 pob0_latency DCR 0x098 pob0_revid DCR 0x09a opb0_bctrl DCR 0x0a8 opb0_bstat DCR 0x0a9 opb0_bearl DCR 0x0aa opb0_bearh DCR 0x0ab opb0_revid DCR 0x0ac ; ; Clocking,P wer Management,and Chip Control ; cpm0_sr DCR 0x0b0 cpm0_er DCR 0x0b1 cpm0_fr DCR 0x0b2 ; ; Universal Interrupt Controllers ; uic0_sr DCR 0x0c0 uic0_er DCR 0x0c2 uic0_cr DCR 0x0c3 uic0_pr DCR 0x0c4 uic0_tr DCR 0x0c5 uic0_msr DCR 0x0c6 uic0_vr DCR 0x0c7 uic0_vcr DCR 0x0c8 uic1_sr DCR 0x0d0 uic1_er DCR 0x0d2 uic1_cr DCR 0x0d3 uic1_pr DCR 0x0d4 uic1_tr DCR 0x0d5 uic1_msr DCR 0x0d6 uic1_vr DCR 0x0d7 uic1_vcr DCR 0x0d8 ; uicb0_sr DCR 0x200 uicb0_er DCR 0x202 uicb0_cr DCR 0x203 uicb0_pr DCR 0x204 uicb0_tr DCR 0x205 uicb0_msr DCR 0x206 uicb0_vr DCR 0x207 uicb0_vcr DCR 0x208 uic2_sr DCR 0x210 uic2_er DCR 0x212 uic2_cr DCR 0x213 uic2_pr DCR 0x214 uic2_tr DCR 0x215 uic2_msr DCR 0x216 uic2_vr DCR 0x217 uic2_vcr DCR 0x218 ; ;Direct Memory Access ; dma0_cr0 DCR 0x100 dma0_ct0 DCR 0x101 dma0_sah0 DCR 0x102 dma0_sal0 DCR 0x103 dma0_dah0 DCR 0x104 dma0_dal0 DCR 0x105 dma0_sgh0 DCR 0x106 dma0_sgl0 DCR 0x107 dma0_cr1 DCR 0x108 dma0_ct1 DCR 0x109 dma0_sah1 DCR 0x10a dma0_sal1 DCR 0x10b dma0_dah1 DCR 0x10c dma0_dal1 DCR 0x10d dma0_sgh1 DCR 0x10e dma0_sgl1 DCR 0x10f dma0_cr2 DCR 0x110 dma0_ct2 DCR 0x111 dma0_sah2 DCR 0x112 dma0_sal2 DCR 0x113 dma0_dah2 DCR 0x114 dma0_dal2 DCR 0x115 dma0_sgh2 DCR 0x116 dma0_sgl2 DCR 0x117 dma0_cr3 DCR 0x118 dma0_ct3 DCR 0x119 dma0_sah3 DCR 0x11a dma0_sal3 DCR 0x11b dma0_dah3 DCR 0x11c dma0_dal3 DCR 0x11d dma0_sgh3 DCR 0x11e dma0_sgl3 DCR 0x11f dma0_sr DCR 0x120 dma0_sgc DCR 0x123 dma0_slp DCR 0x125 dma0_pol DCR 0x126 ; ; Memory Access Layer ; mal0_cfg DCR 0x180 mal0_esr DCR 0x181 mal0_ier DCR 0x182 mal0_txcasr DCR 0x184 mal0_txcarr DCR 0x185 mal0_txeobisr DCR 0x186 mal0_txdeir DCR 0x187 mal0_rxcasr DCR 0x190 mal0_rxcarr DCR 0x191 mal0_rxeobisr DCR 0x192 mal0_rxdeir DCR 0x193 mal0_txctp0r DCR 0x1a0 mal0_txctp1r DCR 0x1a1 mal0_txctp2r DCR 0x1a2 mal0_txctp3r DCR 0x1a3 mal0_rxctp0r DCR 0x1c0 mal0_rxctp1r DCR 0x1c1 mal0_rcbs0 DCR 0x1e0 mal0_rcbs1 DCR 0x1e1 ; ; Level 2 cache ; l2c0_cfg DCR 0x030 l2c0_cmd DCR 0x031 l2c0_addr DCR 0x032 l2c0_data DCR 0x033 l2c0_stat DCR 0x034 l2c0_cver DCR 0x035 l2c0_snp0 DCR 0x036 l2c0_snp1 DCR 0x037 ; cpm1_er DCR 0x0f0 cpm1_fr DCR 0x0f1 cpm1_sr DCR 0x0f2 ; ; Indirectly Accessed DCR's ; ; IDCR1 must be set to SDRAM0_CFGADDR and SDRAM0_CFGDATA ; IDCR2 must be set to EBC0_CFGADDR and EBC0_CFGDATA ; IDCR3 must be set to EBM0_CFGADDR and EBM0_CFGDATA ; IDCR4 must be set to PPM0_CFGADDR and PPM0_CFGDATA ; IDCR5 must be set to CPR0_CFGADDR and CPR0_CFGDATA ; IDCR6 must be set to SDR0_CFGADDR and SDR0_CFGDATA ; ; ; DDR-SDRAM Controller DCRs ; ddr0_00 IDCR1 0x00 ddr0_01 IDCR1 0x01 ddr0_02 IDCR1 0x02 ddr0_03 IDCR1 0x03 ddr0_04 IDCR1 0x04 ddr0_05 IDCR1 0x05 ddr0_06 IDCR1 0x06 ddr0_07 IDCR1 0x07 ddr0_08 IDCR1 0x08 ddr0_09 IDCR1 0x09 ddr0_0a IDCR1 0x0a ddr0_0b IDCR1 0x0b ddr0_0c IDCR1 0x0c ddr0_0d IDCR1 0x0d ddr0_0e IDCR1 0x0e ddr0_0f IDCR1 0x0f ddr0_10 IDCR1 0x10 ddr0_11 IDCR1 0x11 ddr0_12 IDCR1 0x12 ddr0_13 IDCR1 0x13 ddr0_14 IDCR1 0x14 ddr0_15 IDCR1 0x15 ddr0_16 IDCR1 0x16 ddr0_17 IDCR1 0x17 ddr0_18 IDCR1 0x18 ddr0_19 IDCR1 0x19 ddr0_1a IDCR1 0x1a ddr0_1b IDCR1 0x1b ddr0_1c IDCR1 0x1c ddr0_1d IDCR1 0x1d ddr0_1e IDCR1 0x1e ddr0_1f IDCR1 0x1f ddr0_20 IDCR1 0x20 ddr0_21 IDCR1 0x21 ddr0_22 IDCR1 0x22 ddr0_23 IDCR1 0x23 ddr0_24 IDCR1 0x24 ddr0_25 IDCR1 0x25 ddr0_26 IDCR1 0x26 ddr0_27 IDCR1 0x27 ddr0_28 IDCR1 0x28 ddr0_29 IDCR1 0x29 ddr0_2a IDCR1 0x2a ddr0_2b IDCR1 0x2b ddr0_2c IDCR1 0x2c ; ; External Bus Controller DCRs ; ebc0_b0cr IDCR2 0x00 ebc0_b1cr IDCR2 0x01 ebc0_b2cr IDCR2 0x02 ebc0_b3cr IDCR2 0x03 ebc0_b4cr IDCR2 0x04 ebc0_b5cr IDCR2 0x05 ebc0_b6cr IDCR2 0x06 ebc0_b7cr IDCR2 0x07 ebc0_b0ap IDCR2 0x10 ebc0_b1ap IDCR2 0x11 ebc0_b2ap IDCR2 0x12 ebc0_b3ap IDCR2 0x13 ebc0_b4ap IDCR2 0x14 ebc0_b5ap IDCR2 0x15 ebc0_b6ap IDCR2 0x16 ebc0_b7ap IDCR2 0x17 ebc0_bear IDCR2 0x20 ebc0_besr IDCR2 0x21 ebc0_cfg IDCR2 0x23 ebc0_cid IDCR2 0x24 ; ; External Bus Master DCRs ; ebm0_ctl IDCR3 0x00 ebm0_lcnt IDCR3 0x01 ebm0_bear IDCR3 0x02 ebm0_besr IDCR3 0x03 ebm0_bemr IDCR3 0x04 ebm0_uar IDCR3 0x05 ebm0_uam IDCR3 0x06 ebm0_slpmd IDCR3 0x07 ebm0_fair IDCR3 0x08 ebm0_miscsts IDCR3 0x10 ebm0_cid IDCR3 0x11 ; ; PLB Performance Monitor DCRs ; ppm0_isr IDCR4 0x00 ppm0_cr IDCR4 0x02 ppm0_ccr IDCR4 0x03 ppm0_uar IDCR4 0x04 ppm0_lar IDCR4 0x05 ppm0_uamr IDCR4 0x06 ppm0_lamr IDCR4 0x07 ppm0_ridr IDCR4 0x08 ppm0_mcsr0 IDCR4 0x09 ppm0_mcsr1 IDCR4 0x0a ppm0_mcsr2 IDCR4 0x0b ppm0_mcsr3 IDCR4 0x0c ppm0_scsr0 IDCR4 0x11 ppm0_scsr1 IDCR4 0x12 ppm0_scsr2 IDCR4 0x13 ppm0_scsr3 IDCR4 0x14 ppm0_gcsr0 IDCR4 0x19 ppm0_gcsr1 IDCR4 0x1a ppm0_gcsr2 IDCR4 0x1b ppm0_gcsr3 IDCR4 0x1c ppm0_mcr0 IDCR4 0x1d ppm0_mcr1 IDCR4 0x1e ppm0_mcr2 IDCR4 0x1f ppm0_mcr3 IDCR4 0x20 ppm0_scr0 IDCR4 0x25 ppm0_scr1 IDCR4 0x26 ppm0_scr2 IDCR4 0x27 ppm0_scr3 IDCR4 0x28 ppm0_gcr0 IDCR4 0x2d ppm0_gcr1 IDCR4 0x2e ppm0_gcr2 IDCR4 0x2f ppm0_gcr3 IDCR4 0x30 ppm0_dcsr0 IDCR4 0x31 ppm0_dcsr1 IDCR4 0x32 ppm0_dcmxr0 IDCR4 0x33 ppm0_dcmxr1 IDCR4 0x34 ppm0_dcmnr0 IDCR4 0x35 ppm0_dcmnr1 IDCR4 0x36 ppm0_dctvr0 IDCR4 0x37 ppm0_dctvr1 IDCR4 0x38 ppm0_dcotr0 IDCR4 0x39 ppm0_dcotr1 IDCR4 0x3a ; ; Clocking and PowerOn Reset DCR ; cpr0_clkupd IDCR5 0x0020 cpr0_pllc IDCR5 0x0040 cpr0_plld IDCR5 0x0060 cpr0_primad IDCR5 0x0080 cpr0_primbd IDCR5 0x00A0 cpr0_opbd IDCR5 0x00C0 cpr0_perd IDCR5 0x00E0 cpr0_mald IDCR5 0x0100 cpr0_spcid IDCR5 0x0120 cpr0_icfg IDCR5 0x0140 ; ; System DCR ; sdr0_sdstp0 IDCR6 0x0020 sdr0_sdstp1 IDCR6 0x0021 sdr0_pinstp IDCR6 0x0040 sdr0_sdcs IDCR6 0x0060 sdr0_ecid0 IDCR6 0x0080 sdr0_ecid1 IDCR6 0x0081 sdr0_ecid2 IDCR6 0x0082 sdr0_jtag IDCR6 0x00C0 sdr0_ddrdl IDCR6 0x00E0 sdr0_ebc IDCR6 0x0100 sdr0_uart0 IDCR6 0x0120 sdr0_uart1 IDCR6 0x0121 sdr0_cp440 IDCR6 0x0180 sdr0_xcr IDCR6 0x01C0 sdr0_xpllc IDCR6 0x01C1 sdr0_xplld IDCR6 0x01C2 sdr0_srst IDCR6 0x0200 sdr0_srst1 IDCR6 0x0201 sdr0_slpipe IDCR6 0x0220 sdr0_amp IDCR6 0x0240 sdr0_mirq0 IDCR6 0x0260 sdr0_mirq1 IDCR6 0x0261 sdr0_maltbl IDCR6 0x0280 sdr0_malrbl IDCR6 0x02A0 sdr0_maltbs IDCR6 0x02C0 sdr0_malrbs IDCR6 0x02E0 sdr0_pci0 IDCR6 0x0300 sdr0_usb2d0cr IDCR6 0x0320 sdr0_usb2h0cr IDCR6 0x0340 sdr0_cust0 IDCR6 0x4000 sdr0_sdstp2 IDCR6 0x4001 sdr0_cust1 IDCR6 0x4002 sdr0_sdstp3 IDCR6 0x4003 sdr0_pfc0 IDCR6 0x4100 sdr0_pfc1 IDCR6 0x4101 sdr0_pfc2 IDCR6 0x4102 sdr0_usb2phy0cr IDCR6 0x4103 sdr0_plbtr IDCR6 0x4200 sdr0_mfr IDCR6 0x4300 sdr0_usb2host IDCR6 0x4600 ; ; PCI Registers ; PCIC0_CFGADDR PMM2 0x0000 PCIC0_CFGDATA PMM2 0x0004 ; PCIC0_CACHELS MM 0x8000000C 32 PCIC0_BRDGOPT1 MM 0x8000004A 32 PCIC0_VENDID MM 0x80000000 32 PCIC0_DEVID MM 0x80000002 32 PCIC0_CMD MM 0x80000004 32 PCIC0_STATUS MM 0x80000006 32 PCIC0_REVID MM 0x80000008 32 PCIC0_CLS MM 0x80000009 32 PCIC0_LATTIM MM 0x8000000D 32 PCIC0_HDTYPE MM 0x8000000E 32 PCIC0_BIST MM 0x8000000F 32 PCIC0_PTM1BAR MM 0x80000014 32 PCIC0_PTM2BAR MM 0x80000018 32 PCIC0_SBSYSVID MM 0x8000002C 32 PCIC0_SBSYSID MM 0x8000002E 32 PCIC0_CAP MM 0x80000034 32 PCIC0_INTLN MM 0x8000003C 32 PCIC0_INTPN MM 0x8000003D 32 PCIC0_MINGNT MM 0x8000003E 32 PCIC0_MAXLTNCY MM 0x8000003F 32 PCIC0_ICS MM 0x80000044 32 PCIC0_ERREN MM 0x80000048 32 PCIC0_ERRSTS MM 0x80000049 32 PCIC0_PLBBESR0 MM 0x8000004C 32 PCIC0_PLBBESR1 MM 0x80000050 32 PCIC0_PLBBEAR MM 0x80000054 32 PCIC0_CAPID MM 0x80000058 32 PCIC0_NEXTIPTR MM 0x80000059 32 PCIC0_PMC MM 0x8000005A 32 PCIC0_PMCSR MM 0x8000005C 32 PCIC0_PMCSRBSE MM 0x8000005E 32 PCIC0_DATA MM 0x8000005F 32 PCIC0_BRDGOPT2 MM 0x80000060 32 PCIC0_PMSCRR MM 0x80000064 32 ; PCIL0_PMM0LA PMM3 0x0000 PCIL0_PMM0MA PMM3 0x0004 PCIL0_PMM0PCILA PMM3 0x0008 PCIL0_PMM0PCIHA PMM3 0x000C PCIL0_PMM1LA PMM3 0x0010 PCIL0_PMM1MA PMM3 0x0014 PCIL0_PMM1PCILA PMM3 0x0018 PCIL0_PMM1PCIHA PMM3 0x001C PCIL0_PMM2LA PMM3 0x0020 PCIL0_PMM2MA PMM3 0x0024 PCIL0_PMM2PCILA PMM3 0x0028 PCIL0_PMM2PCIHA PMM3 0x002C PCIL0_PTM1MS PMM3 0x0030 PCIL0_PTM1LA PMM3 0x0034 PCIL0_PTM2MS PMM3 0x0038 PCIL0_PTM2LA PMM3 0x003C ; ; GPIO Registers ; GPIO0_IR MM 0xEF600B1C 32 GPIO0_ISR1H MM 0xEF600B34 32 GPIO0_ISR1L MM 0xEF600B30 32 GPIO0_ISR2H MM 0xEF600B3C 32 GPIO0_ISR2L MM 0xEF600B38 32 GPIO0_ISR3H MM 0xEF600B44 32 GPIO0_ISR3L MM 0xEF600B40 32 GPIO0_ODR MM 0xEF600B18 32 GPIO0_OR MM 0xEF600B00 32 GPIO0_OSRH MM 0xEF600B0C 32 GPIO0_OSRL MM 0xEF600B08 32 GPIO0_RR1 MM 0xEF600B20 32 GPIO0_RR2 MM 0xEF600B24 32 GPIO0_RR3 MM 0xEF600B28 32 GPIO0_TCR MM 0xEF600B04 32 GPIO0_TSRH MM 0xEF600B14 32 GPIO0_TSRL MM 0xEF600B10 32 GPIO1_IR MM 0xEF600C1C 32 GPIO1_ISR1H MM 0xEF600C34 32 GPIO1_ISR1L MM 0xEF600C30 32 GPIO1_ISR2H MM 0xEF600C3C 32 GPIO1_ISR2L MM 0xEF600C38 32 GPIO1_ISR3H MM 0xEF600C44 32 GPIO1_ISR3L MM 0xEF600C40 32 GPIO1_ODR MM 0xEF600C18 32 GPIO1_OR MM 0xEF600C00 32 GPIO1_OSRH MM 0xEF600C0C 32 GPIO1_OSRL MM 0xEF600C08 32 GPIO1_RR1 MM 0xEF600C20 32 GPIO1_RR2 MM 0xEF600C24 32 GPIO1_RR3 MM 0xEF600C28 32 GPIO1_TCR MM 0xEF600C04 32 GPIO1_TSRH MM 0xEF600C14 32 GPIO1_TSRL MM 0xEF600C10 32